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authorli feng <li1.feng@intel.com>2021-09-28 20:29:40 -0700
committerCommit Bot <commit-bot@chromium.org>2021-10-02 00:30:17 +0000
commit9aadff4307ab45b3dde6fcec26edc14136bc9dfe (patch)
tree080a420261ca06f1eec0f71aeb2632d9d840fde2
parent533640b6d2ce1189b8c0559ec69e1d64202d2c8b (diff)
downloadchrome-ec-9aadff4307ab45b3dde6fcec26edc14136bc9dfe.tar.gz
adlrvpp_ite: enable internal pull-up for GPGO
It is observed that PD port 3 has TCPC interrupt storm, the TCPC interrupt pin GPJ3 stays active low even no interrupt coming. The root cause is GPJ3 is configured as voltage comparator by GPG0 after EC power on. Remove GPGO external pull-up resistor to fix this issue. GPGO is PD port 1 TCPC interrupt pin, enable internal pull-up since external pull-up resistor is removed. BUG=b:200265672 BRANCH=none TEST=on ADL-P DDR5 RVP, apply CL:3111455 and CL:3114705 to enable low power mode. Don't see interrupt storm on PD port 3. Connect Gatkex to PD port 1, enter USB4 mode successfully. Connect Gatkex to PD port 3, enter USB4 mode successfully. Signed-off-by: li feng <li1.feng@intel.com> Change-Id: If66011ca86a268556ce69bd06f938c92407217aa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3193511 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Commit-Queue: caveh jalali <caveh@chromium.org>
-rw-r--r--board/adlrvpp_ite/gpio.inc7
1 files changed, 6 insertions, 1 deletions
diff --git a/board/adlrvpp_ite/gpio.inc b/board/adlrvpp_ite/gpio.inc
index f4db15c4d5..59af6cf877 100644
--- a/board/adlrvpp_ite/gpio.inc
+++ b/board/adlrvpp_ite/gpio.inc
@@ -48,8 +48,13 @@ UNIMPLEMENTED(USBC_TCPC_ALRT_P0)
GPIO(NC_USBC_TCPC_ALRT_P0, PIN(I, 7), GPIO_INPUT)
GPIO_INT(USBC_TCPC_PPC_ALRT_P0, PIN(J, 5), GPIO_INT_FALLING, ppc_interrupt)
+/*
+ * b:200265672 External pull-up resistor of port 1 is removed to fix port 3
+ * TCPC interrupt issue. So add internal pull-up for port 1 instead.
+ * This change is only applied to ITE chip.
+ */
#if defined(HAS_TASK_PD_C1)
-GPIO_INT(USBC_TCPC_ALRT_P1, PIN(G, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USBC_TCPC_ALRT_P1, PIN(G, 0), GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event)
GPIO_INT(USBC_TCPC_PPC_ALRT_P1, PIN(C, 4), GPIO_INT_FALLING, ppc_interrupt)
#else
GPIO(USBC_TCPC_ALRT_P1, PIN(G, 0), GPIO_INPUT)