diff options
author | Keith Short <keithshort@chromium.org> | 2019-10-31 13:43:41 -0600 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2019-11-01 04:36:51 +0000 |
commit | 36d36bafc2ff53efbed0fb1638c82fca07e17dc1 (patch) | |
tree | bf6ee90a6da42b09693340da773b0c6adbae480d | |
parent | 65294881b3aee9f47b649cc9a2320a1c3f5ab9f9 (diff) | |
download | chrome-ec-36d36bafc2ff53efbed0fb1638c82fca07e17dc1.tar.gz |
volteer: Add manual power sequencing
As backup if board driven power sequencing doesn't work, implement EC
controlled power sequencing on Volteer.
BUG=b:140556273
BRANCH=none
TEST=make buildall
TEST=make BOARD=volteer VOLTEER_POWER_SEQUENCE=y
Change-Id: I62e30e5f153085e2e6c26005a77e2e1abe981b0a
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881754
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
-rw-r--r-- | board/volteer/board.h | 2 | ||||
-rw-r--r-- | board/volteer/build.mk | 17 | ||||
-rw-r--r-- | board/volteer/gpio.inc | 19 | ||||
-rw-r--r-- | board/volteer/power_sequence.c | 183 |
4 files changed, 220 insertions, 1 deletions
diff --git a/board/volteer/board.h b/board/volteer/board.h index 9a636da471..b7e7671aff 100644 --- a/board/volteer/board.h +++ b/board/volteer/board.h @@ -74,6 +74,8 @@ #include "gpio_signal.h" #include "registers.h" +/* TODO: b/143375057 - Remove this code after power on. */ +void c10_gate_change(enum gpio_signal signal); #endif /* !__ASSEMBLER__ */ diff --git a/board/volteer/build.mk b/board/volteer/build.mk index 72645a86cd..9ebde9ae1b 100644 --- a/board/volteer/build.mk +++ b/board/volteer/build.mk @@ -11,4 +11,21 @@ CHIP_FAMILY:=npcx7 CHIP_VARIANT:=npcx7m6fc BASEBOARD:=volteer +# TODO: b/143375057 - Remove this code after power on. +# +# Temporary for board power on. Provide a Volteer specific make option +# to enable the power signal GPIOs that are not stuffed by default. This +# is a backup if board logic power sequencing needs to be adjusted. +# +# Set the following variable to 'y' to enable the Volteer optional power signals +VOLTEER_POWER_SEQUENCE= +ifneq (,$(VOLTEER_POWER_SEQUENCE)) +CFLAGS_BASEBOARD+=-DVOLTEER_POWER_SEQUENCE +endif + +# Force changes to VOLTEER_POWER_SEQUENCE variable to trigger a full build. +ENV_VARS := VOLTEER_POWER_SEQUENCE + + board-y=board.o +board-$(VOLTEER_POWER_SEQUENCE)+=power_sequence.o diff --git a/board/volteer/gpio.inc b/board/volteer/gpio.inc index 7f59cc0ab5..c459a8d589 100644 --- a/board/volteer/gpio.inc +++ b/board/volteer/gpio.inc @@ -14,6 +14,11 @@ GPIO_INT(EC_WP_L, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) GPIO_INT(H1_EC_PWR_BTN_ODL, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt) GPIO_INT(ACOK_OD, PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt) +/* Optional power sequencing interrupts */ +#ifdef VOLTEER_POWER_SEQUENCE +GPIO_INT(CPU_C10_GATE_L, PIN(6, 7), GPIO_INT_BOTH, c10_gate_change) +#endif + /* Power sequencing interrupts */ GPIO_INT(SLP_S0_L, PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt) #ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3 @@ -38,6 +43,19 @@ GPIO(EN_PP5000_A, PIN(A, 4), GPIO_OUT_LOW) /* The EC does not buffer this signal on Volteer. */ UNIMPLEMENTED(PCH_DSW_PWROK) +#ifdef VOLTEER_POWER_SEQUENCE +/* Optional power sequencing signals that are not stuffed by default */ +GPIO(EN_DRAM_VDDQ, PIN(F, 2), GPIO_OUT_LOW) +GPIO(EN_PP1050_STG, PIN(C, 0), GPIO_OUT_LOW) +GPIO(EN_PP5000_USB_AG, PIN(A, 7), GPIO_OUT_LOW) +GPIO(EN_PP1800_A, PIN(8, 3), GPIO_OUT_LOW) +GPIO(EN_PPVAR_VCCIN_AUX, PIN(8, 1), GPIO_OUT_LOW) +GPIO(EN_PP1050_ST_S0, PIN(3, 4), GPIO_OUT_LOW) +GPIO(EN_VNN_BYPASS, PIN(B, 0), GPIO_OUT_LOW) +GPIO(EN_PP1050_BYPASS, PIN(9, 7), GPIO_OUT_LOW) +GPIO(EN_DRAM_VDD1, PIN(9, 6), GPIO_OUT_LOW) +#endif + /* Other wake sources */ /* * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an @@ -58,7 +76,6 @@ GPIO(EC_PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) GPIO(EC_PCH_WAKE_ODL, PIN(7, 4), GPIO_ODR_HIGH) GPIO(EC_ENTERING_RW, PIN(E, 3), GPIO_OUT_LOW) GPIO(EC_PROCHOT_ODL, PIN(6, 3), GPIO_ODR_HIGH) -GPIO(CPU_C10_GATE_L, PIN(6, 7), GPIO_INPUT) /* TODO - b/141322107 - implement if board power sequencing insufficient */ GPIO(SYS_RST_ODL, PIN(C, 5), GPIO_ODR_HIGH) GPIO(EC_PCH_INT_ODL, PIN(D, 6), GPIO_ODR_HIGH) /* TODO - b/140557015 - implement with MKBD sensor events */ diff --git a/board/volteer/power_sequence.c b/board/volteer/power_sequence.c new file mode 100644 index 0000000000..bf1be81b6a --- /dev/null +++ b/board/volteer/power_sequence.c @@ -0,0 +1,183 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * Volteer board-specific power sequencing + * Power sequencing is largely done by the platform automatically. + * However, if platform power sequencing is buggy or needs tuning, + * resistors can be stuffed on the board to allow the EC full control over + * the power sequencing. + */ + +#include "assert.h" +#include "chipset.h" +#include "console.h" +#include "gpio.h" +#include "hooks.h" +#include "system.h" + +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define GPIO_SET_VERBOSE(signal, value) \ + gpio_set_level_verbose(CC_CHIPSET, signal, value) + +static void board_wakeup(void) +{ + CPRINTS("%s", __func__); + /* + * PP5000_USB_AG - normally enabled automatically by EN_3300_AG which + * is connected to the PSL_OUT of the Nuvoton. + * + * Assert the signal high during wakeup, deassert at hibernate + */ + GPIO_SET_VERBOSE(GPIO_EN_PP5000_USB_AG, 1); +} +DECLARE_HOOK(HOOK_INIT, board_wakeup, HOOK_PRIO_DEFAULT); + +__override void board_hibernate_late(void) +{ + CPRINTS("%s", __func__); + /* Disable PP5000_USB_AG on hibernate */ + GPIO_SET_VERBOSE(GPIO_EN_PP5000_USB_AG, 0); +} + +/* Called during S5 -> S3 transition */ +static void board_chipset_startup(void) +{ + CPRINTS("%s", __func__); + + /* + * + */ + + /* + * Power on 1.8V rail, + * tPCH06, minimum 200us from P-P3300_DSW stable to before + * VCCPRIM_1P8 starting up. + * + * The transition to S5 and S3 is gated by SLP_SUS#, which Tiger Lake + * internally delays a minimum of 95 ms from DSW_PWROK. So no delay + * needed here. + */ + GPIO_SET_VERBOSE(GPIO_EN_PP1800_A, 1); + + /* + * Power on VCCIN Aux - no delay specified, but must follow VCCPRIM_1P8 + */ + GPIO_SET_VERBOSE(GPIO_EN_PPVAR_VCCIN_AUX, 1); + + /* + * Power on bypass rails - must be turned on after VCCIN aux + * + * tPCH34, maximum 50 ms from SLP_SUS# de-assertion to completion of + * primary and bypass rail, no minimum specified. + */ + GPIO_SET_VERBOSE(GPIO_EN_VNN_BYPASS, 1); + GPIO_SET_VERBOSE(GPIO_EN_PP1050_BYPASS, 1); + + /* + * Power on VCCST - must be gated by SLP_S3#. No order with respect to + * other power signals specified. + */ + GPIO_SET_VERBOSE(GPIO_EN_PP1050_ST_S0, 1); + + /* + * Power on DDR rails + * No delay needed - SLP_S4# already guaranteed to be de-asserted. + * VDDQ must ramp after VPP (VDD1) for DDR4/LPDDR4 systems. + */ + GPIO_SET_VERBOSE(GPIO_EN_DRAM_VDD1, 1); + GPIO_SET_VERBOSE(GPIO_EN_DRAM_VDDQ, 1); +} +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT); + +/* Called during S3 -> S0 and S0ix -> S0 transition */ +static void board_chipset_resume(void) +{ + CPRINTS("%s", __func__); + /* + * Power on VCCSTG rail to Tiger Lake, no PG signal available + */ + GPIO_SET_VERBOSE(GPIO_EN_PP1050_STG, 1); +} +DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); + + +/* Called during S0 -> S0ix transition */ +static void board_chipset_suspend(void) +{ + CPRINTS("%s", __func__); + /* Power down VCCSTG rail */ + GPIO_SET_VERBOSE(GPIO_EN_PP1050_STG, 0); +} +DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); + +/* Called during S3 -> S5 transition */ +static void board_chipset_shutdown(void) +{ + CPRINTS("%s", __func__); + + /* + * S0 to G3 sequence 1 of 2 (shared between Deep Sx and non-Deep Sx) + * TigerLake Rail Net Name + * VCCSTG PP1050_STG_S0 + * DDR_VDDQ PP0600_VDDQ + * VCCST PP1050_ST_S0 + * DDR_VPP PP1800_DRAM + */ + GPIO_SET_VERBOSE(GPIO_EN_PP1050_STG, 0); + GPIO_SET_VERBOSE(GPIO_EN_DRAM_VDDQ, 0); + GPIO_SET_VERBOSE(GPIO_EN_PP1050_ST_S0, 0); + GPIO_SET_VERBOSE(GPIO_EN_DRAM_VDD1, 0); + + /* + * S0 to G3 sequence 2 of 2 (non-Deep Sx) + * TigerLake Name Net Name + * VCCPRIM_3P3 PP3300_A + * VCCDSW_3P3 VCCDSW_3P3 (PP3300_A) + * V5.0A PP5000_A + * VCCPRIM_1P8 PP1800_A + * VCCIN_AUX PPVAR_VCCIN_AUX + * VNN_BYPASS PPVAR_VNN_BYPASS + * V1.05A_BYPASS PP1050_A_BYPASS + */ + + /* Ice Lake shutdown already sequences first 3 rails above. */ + chipset_force_shutdown(CHIPSET_SHUTDOWN_G3); + + GPIO_SET_VERBOSE(GPIO_EN_PP1800_A, 0); + GPIO_SET_VERBOSE(GPIO_EN_PPVAR_VCCIN_AUX, 0); + GPIO_SET_VERBOSE(GPIO_EN_VNN_BYPASS, 0); + GPIO_SET_VERBOSE(GPIO_EN_PP1050_BYPASS, 0); +} +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT); + +/** + * Handle C10_GATE transitions - see VCCSTG enable logic (figure 232, page 406) + * in Tiger Lake PDG, revision 1.0. + * + * TODO: b/141322107 - This function can be promoted to common TigerLake power + * file if CPU_C10_GATE_L support provided by the platform is not sufficient. + */ +void c10_gate_change(enum gpio_signal signal) +{ + /* Pass through CPU_C10_GATE_L as enable for VCCSTG rail */ + int c10_gate_in; + int vccstg_out; + + ASSERT(signal == GPIO_CPU_C10_GATE_L); + + c10_gate_in = gpio_get_level(signal); + vccstg_out = gpio_get_level(GPIO_EN_PP1050_STG); + + if (vccstg_out == c10_gate_in) + return; + + gpio_set_level(GPIO_EN_PP1050_STG, c10_gate_in); +} + + + + + |