zephyr: Initial image for npcx_evb/npcx7

Initial image for npcx_evb/npcx7 supporting basic UART functionality
and basic commands.

BUG=none
BRANCH=none
TEST=test basic console functionality on npcx7_evb

Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Ibdf1ce98b6ad747dc649b82f12e555e63569036a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3033230
Reviewed-by: Yuval Peress <peress@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>

10 files changed, 177 insertions, 0 deletions

diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.board b/zephyr/boards/arm/npcx_evb/Kconfig.board
new file mode 100644
index 0000000000..d7cdd067da
--- /dev/null
+++ b/zephyr/boards/arm/npcx_evb/Kconfig.board
@@ -0,0 +1,12 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Note: this Zephyr board more closely represents the Chrome OS
+# concept of a baseboard.  Zephyr boards and Chrome OS boards do not
+# have a 1:1 mapping.
+config BOARD_NPCX7_EVB
+	bool "NPCX7 Evaluation Board"
+	depends on SOC_NPCX7M6FB || SOC_NPCX7M6FC || SOC_NPCX7M7FC
+	# Allow generating initial 0 line coverage.
+	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.defconfig b/zephyr/boards/arm/npcx_evb/Kconfig.defconfig
new file mode 100644
index 0000000000..81268a4636
--- /dev/null
+++ b/zephyr/boards/arm/npcx_evb/Kconfig.defconfig
@@ -0,0 +1,6 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD
+	default "npcx7_evb" if BOARD_NPCX7_EVB
diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb.dts b/zephyr/boards/arm/npcx_evb/npcx7_evb.dts
new file mode 100644
index 0000000000..c20589d637
--- /dev/null
+++ b/zephyr/boards/arm/npcx_evb/npcx7_evb.dts
@@ -0,0 +1,22 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/nuvoton/npcx7.dtsi>
+
+/*
+ * #include <nuvoton/npcx7m6fb.dtsi>
+ * #include <nuvoton/npcx7m6fc.dtsi>
+ * #include <nuvoton/npcx7m7fc.dtsi>
+ */
+#include <nuvoton/npcx7m6fc.dtsi>
+#include "npcx_evb.dtsi"
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */
+};
diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig
new file mode 100644
index 0000000000..7491ae09df
--- /dev/null
+++ b/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig
@@ -0,0 +1,34 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_NPCX7=y
+# NPCX7 soc list
+#  CONFIG_SOC_NPCX7M6FB
+#  CONFIG_SOC_NPCX7M6FC
+#  CONFIG_SOC_NPCX7M7FC
+CONFIG_SOC_NPCX7M6FC=y
+
+# Platform Configuration
+CONFIG_BOARD_NPCX7_EVB=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Pinmux Driver
+CONFIG_PINMUX=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
diff --git a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi b/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi
new file mode 100644
index 0000000000..65c1ab7e68
--- /dev/null
+++ b/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi
@@ -0,0 +1,17 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	model = "Nuvoton NPCX Evaluation Board";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,flash = &flash0;
+	};
+};
diff --git a/zephyr/projects/npcx_evb/npcx7/CMakeLists.txt b/zephyr/projects/npcx_evb/npcx7/CMakeLists.txt
new file mode 100644
index 0000000000..b48b5d795d
--- /dev/null
+++ b/zephyr/projects/npcx_evb/npcx7/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+set(BOARD_ROOT "${CMAKE_CURRENT_LIST_DIR}/..")
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(npcx7)
+
+zephyr_include_directories(include)
diff --git a/zephyr/projects/npcx_evb/npcx7/gpio.dts b/zephyr/projects/npcx_evb/npcx7/gpio.dts
new file mode 100644
index 0000000000..5de0a5e422
--- /dev/null
+++ b/zephyr/projects/npcx_evb/npcx7/gpio.dts
@@ -0,0 +1,10 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-gpios {
+		compatible = "named-gpios";
+	};
+};
diff --git a/zephyr/projects/npcx_evb/npcx7/include/gpio_map.h b/zephyr/projects/npcx_evb/npcx7/include/gpio_map.h
new file mode 100644
index 0000000000..61258d1184
--- /dev/null
+++ b/zephyr/projects/npcx_evb/npcx7/include/gpio_map.h
@@ -0,0 +1,32 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_GPIO_MAP_H
+#define __ZEPHYR_GPIO_MAP_H
+
+#include <devicetree.h>
+#include <gpio_signal.h>
+
+#define GPIO_ENTERING_RW	GPIO_UNIMPLEMENTED
+#define GPIO_WP_L		GPIO_UNIMPLEMENTED
+
+/*
+ * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
+ *
+ * Each GPIO_INT requires three parameters:
+ *   gpio_signal - The enum gpio_signal for the interrupt gpio
+ *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
+ *   handler - The platform/ec interrupt handler.
+ *
+ * Ensure that this files includes all necessary headers to declare all
+ * referenced handler functions.
+ *
+ * For example, one could use the follow definition:
+ * #define EC_CROS_GPIO_INTERRUPTS \
+ *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
+ */
+#define EC_CROS_GPIO_INTERRUPTS
+
+#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/npcx_evb/npcx7/prj.conf b/zephyr/projects/npcx_evb/npcx7/prj.conf
new file mode 100644
index 0000000000..d7e60fc6bc
--- /dev/null
+++ b/zephyr/projects/npcx_evb/npcx7/prj.conf
@@ -0,0 +1,22 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_BRINGUP=y
+CONFIG_SHIMMED_TASKS=y
+
+CONFIG_CROS_KB_RAW_NPCX=n
+
+CONFIG_AP=n
+CONFIG_PLATFORM_EC_ADC=n
+CONFIG_PLATFORM_EC_I2C=n
+CONFIG_PLATFORM_EC_KEYBOARD=n
+CONFIG_PLATFORM_EC_VBOOT=n
+CONFIG_PLATFORM_EC_VSTORE=n
+
+# Zephyr feature
+CONFIG_ASSERT=y
+CONFIG_SHELL_MINIMAL=n
+CONFIG_LOG=y
diff --git a/zephyr/projects/npcx_evb/npcx7/zmake.yaml b/zephyr/projects/npcx_evb/npcx7/zmake.yaml
new file mode 100644
index 0000000000..10cb8dffb7
--- /dev/null
+++ b/zephyr/projects/npcx_evb/npcx7/zmake.yaml
@@ -0,0 +1,11 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+board: npcx7_evb
+dts-overlays:
+  - gpio.dts
+supported-zephyr-versions:
+  - v2.6
+toolchain: coreboot-sdk
+output-type: npcx