zephyr: enable related configs for flash driver on it8xxx2

These flash related configs have to be enabled for the flash driver
of it8xxx2.

This CL also distinguishes the flash configs into header file of
it8xxx2 and npcx.

BUG=b:187192628
BRANCH=none
TEST=zmake -lDEBUG configure -b -B zephyr/build_ite \
zephyr/projects/it8xxx2_evb
     zmake -lDEBUG configure -b -B zephyr/build_volteer \
zephyr/projects/volteer/volteer

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Change-Id: Ic6a2e89a24676d6ac484a389c938ab0692971be0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2952280
Reviewed-by: Keith Short <keithshort@chromium.org>

4 files changed, 104 insertions, 18 deletions

diff --git a/zephyr/Kconfig.flash b/zephyr/Kconfig.flash
index 7ec8be82a5..f6a8b2d103 100644
--- a/zephyr/Kconfig.flash
+++ b/zephyr/Kconfig.flash
@@ -6,7 +6,7 @@ if PLATFORM_EC_FLASH_CROS
 
 config PLATFORM_EC_SPI_FLASH_REGS
 	bool "Enable SPI flash registers"
-	default y
+	default y if SOC_FAMILY_NPCX
 	help
 	  Enables flash registers for SPI flash (both internal and external).
 	  When enabled, two new functions will become available: (1) a function
@@ -61,22 +61,47 @@ config PLATFORM_EC_CONSOLE_CMD_SYSJUMP
 	  copying the image data from flash to ram, then jumping to the image's
 	  entry point.
 
+choice PLATFORM_EC_STORAGE_TYPE
+       prompt "Code storage type"
+       default PLATFORM_EC_EXTERNAL_STORAGE if SOC_FAMILY_NPCX
+       default PLATFORM_EC_INTERNAL_STORAGE if SOC_FAMILY_RISCV_ITE
+       help
+         Sets the EC code storage type.
+
 config PLATFORM_EC_EXTERNAL_STORAGE
 	bool "Flash is stored external to the EC"
-	default y if SOC_FAMILY_NPCX
 	help
 	  This indicates that the EC's flash is stored separately and is it
 	  not possible execute directly from it. Code must be loaded from
 	  the flash into internal SRAM before it can be executed. It is still
 	  possible to read and write the flash.
 
+config PLATFORM_EC_INTERNAL_STORAGE
+	bool "Flash is stored internal to the EC"
+	help
+	  This indicates that the EC code can reside on internal storage.
+	  This option implies XIP(eXecute-In-Place) semantics.
+	  i.e. code is being fetched directly from storage media.
+
+endchoice
+
 config PLATFORM_EC_MAPPED_STORAGE
 	bool "Flash is mapped into the EC's address space"
-	default y if SOC_FAMILY_NPCX
+	default y if SOC_FAMILY_NPCX || SOC_FAMILY_RISCV_ITE
 	help
 	  This indicates that the EC's flash is directly mapped into
 	  its address space. This makes it easier to read and write the flash.
 	  If this is not defined, the flash driver must implement
 	  flash_physical_read().
 
+config PLATFORM_EC_FLASH_PSTATE
+	bool "Store persistent write protect for the flash inside"
+	default y if SOC_FAMILY_RISCV_ITE
+	help
+	  Store persistent write protect for the flash inside the flash data
+	  itself.  This allows ECs with internal flash to emulate something
+	  closer to a SPI flash write protect register.  If this is not
+	  defined, write protect state is maintained solely by the physical
+	  flash driver.
+
 endif # PLATFORM_EC_FLASH_CROS
diff --git a/zephyr/shim/chip/it8xxx2/include/flash_chip.h b/zephyr/shim/chip/it8xxx2/include/flash_chip.h
new file mode 100644
index 0000000000..ff975ac439
--- /dev/null
+++ b/zephyr/shim/chip/it8xxx2/include/flash_chip.h
@@ -0,0 +1,38 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_FLASH_CHIP_H
+#define __CROS_EC_FLASH_CHIP_H
+
+/* Flash size */
+#define CONFIG_FLASH_SIZE_BYTES         DT_REG_SIZE(DT_NODELABEL(flash0))
+/* Program is run directly from storage */
+#define CONFIG_MAPPED_STORAGE_BASE      DT_REG_ADDR(DT_NODELABEL(flash0))
+/*
+ * One page program instruction allows maximum 256 bytes (a page) of data
+ * to be programmed.
+ */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE   256
+/* Minimum write size */
+#define CONFIG_FLASH_WRITE_SIZE         DT_PROP(DT_INST(0, soc_nv_flash), \
+						write_block_size)
+/* Erase bank size */
+#define CONFIG_FLASH_ERASE_SIZE         DT_PROP(DT_INST(0, soc_nv_flash), \
+						erase_block_size)
+/* Protect bank size */
+#define CONFIG_FLASH_BANK_SIZE          CONFIG_FLASH_ERASE_SIZE
+
+#define CONFIG_RO_STORAGE_OFF           0x0
+#define CONFIG_RW_STORAGE_OFF           0x0
+
+/*
+ * The EC uses the one bank of flash to emulate a SPI-like write protect
+ * register with persistent state.
+ */
+#define CONFIG_FW_PSTATE_SIZE           CONFIG_FLASH_BANK_SIZE
+#define CONFIG_FW_PSTATE_OFF            (CONFIG_FLASH_SIZE_BYTES / 2 - \
+						CONFIG_FW_PSTATE_SIZE)
+
+#endif /* __CROS_EC_FLASH_CHIP_H */
diff --git a/zephyr/shim/chip/npcx/include/flash_chip.h b/zephyr/shim/chip/npcx/include/flash_chip.h
new file mode 100644
index 0000000000..c8b3426e69
--- /dev/null
+++ b/zephyr/shim/chip/npcx/include/flash_chip.h
@@ -0,0 +1,28 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_FLASH_CHIP_H
+#define __CROS_EC_FLASH_CHIP_H
+
+#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
+#ifdef CONFIG_FLASH_SIZE
+#define CONFIG_FLASH_SIZE_BYTES	(CONFIG_FLASH_SIZE * 1024)
+#else
+#define CONFIG_FLASH_SIZE_BYTES 0x0
+#endif
+
+/* TODO(b:176490413): use DT_PROP(DT_INST(inst, DT_DRV_COMPAT), size) ? */
+#define CONFIG_MAPPED_STORAGE_BASE 0x64000000
+#define CONFIG_FLASH_WRITE_SIZE		0x1  /* minimum write size */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256   /* one page size for write */
+#define CONFIG_FLASH_ERASE_SIZE	0x10000
+#define CONFIG_FLASH_BANK_SIZE		CONFIG_FLASH_ERASE_SIZE
+
+/* RO image resides at start of protected region, right after header */
+#define CONFIG_RO_STORAGE_OFF	CONFIG_RO_HDR_SIZE
+
+#define CONFIG_RW_STORAGE_OFF 0
+
+#endif /* __CROS_EC_FLASH_CHIP_H */
diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h
index 1d49fb504e..512097baac 100644
--- a/zephyr/shim/include/config_chip.h
+++ b/zephyr/shim/include/config_chip.h
@@ -328,23 +328,14 @@
 
 /* Flash settings */
 #undef CONFIG_EXTERNAL_STORAGE
+#undef CONFIG_INTERNAL_STORAGE
 #undef CONFIG_MAPPED_STORAGE
 #undef CONFIG_FLASH_PSTATE
 #undef CONFIG_FLASH_SIZE_BYTES
 #ifdef CONFIG_PLATFORM_EC_FLASH_CROS
+#include "flash_chip.h"
 #define CONFIG_FLASH_CROS
 #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-#ifdef CONFIG_FLASH_SIZE
-#define CONFIG_FLASH_SIZE_BYTES	(CONFIG_FLASH_SIZE * 1024)
-#else
-#define CONFIG_FLASH_SIZE_BYTES 0x0
-#endif
-/* TODO(b:176490413): use DT_PROP(DT_INST(inst, DT_DRV_COMPAT), size) ? */
-#define CONFIG_MAPPED_STORAGE_BASE 0x64000000
-#define CONFIG_FLASH_WRITE_SIZE		0x1  /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256   /* one page size for write */
-#define CONFIG_FLASH_ERASE_SIZE	0x10000
-#define CONFIG_FLASH_BANK_SIZE		CONFIG_FLASH_ERASE_SIZE
 
 /* Internal, don't use outside this header */
 #define _BINMAN_RO_PATH DT_PATH(binman, wp_ro)
@@ -355,20 +346,24 @@
 #define CONFIG_EC_WRITABLE_STORAGE_OFF DT_PROP(_BINMAN_RW_PATH, offset)
 #define CONFIG_EC_WRITABLE_STORAGE_SIZE DT_PROP(_BINMAN_RW_PATH, size)
 
-/* RO image resides at start of protected region, right after header */
-#define CONFIG_RO_STORAGE_OFF	CONFIG_RO_HDR_SIZE
-
-#define CONFIG_RW_STORAGE_OFF 0
 #define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE
 
 #ifdef CONFIG_PLATFORM_EC_EXTERNAL_STORAGE
 #define CONFIG_EXTERNAL_STORAGE
 #endif
 
+#ifdef CONFIG_PLATFORM_EC_INTERNAL_STORAGE
+#define CONFIG_INTERNAL_STORAGE
+#endif
+
 #ifdef CONFIG_PLATFORM_EC_MAPPED_STORAGE
 #define CONFIG_MAPPED_STORAGE
 #endif
 
+#ifdef CONFIG_PLATFORM_EC_FLASH_PSTATE
+#define CONFIG_FLASH_PSTATE
+#endif
+
 #undef CONFIG_CMD_FLASH
 #ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH
 #define CONFIG_CMD_FLASH