diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2019-12-20 13:18:21 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-12-23 03:03:22 +0000 |
| commit | e3f009f7773cc40f86b01326fe451e797b3f5080 (patch) | |
| tree | cfea22a2521bf09e56cf4212cf9a2f9249c2d8e5 | |
| parent | b462358fe122b51cdad99740329e6034c35bf4a0 (diff) | |
| download | chrome-ec-e3f009f7773cc40f86b01326fe451e797b3f5080.tar.gz | |
chip/it8xxx2: Don't let internal flash go into deep power down mode
We got an issue on IT83202BX that flash won't be able to wake up
correctly in EC low power mode when WRST# is asserted.
This issue might cause cold reset failure so we made this change
to fix it.
BUG=none
BRANCH=none
TEST=hibernate EC and then press servo board's COLD_RST_L to reset EC.
EC reboots.
Change-Id: Ide3a240e1fe62d712536c69d8f390241e67144f6
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1973974
Reviewed-by: Jett Rink <jettrink@chromium.org>
| -rw-r--r-- | chip/it83xx/clock.c | 24 | ||||
| -rw-r--r-- | chip/it83xx/config_chip_it8xxx2.h | 2 | ||||
| -rw-r--r-- | chip/it83xx/registers.h | 2 |
3 files changed, 28 insertions, 0 deletions
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index 468037f0e9..7c679bffbe 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -141,6 +141,30 @@ void __ram_code clock_ec_pll_ctrl(enum ec_pll_ctrl mode) IT83XX_ECPM_PLLCTRL = mode; /* for deep doze / sleep mode */ IT83XX_ECPM_PLLCTRL = mode; + +#ifdef IT83XX_CHIP_FLASH_NO_DEEP_POWER_DOWN + /* + * WORKAROUND: this workaround is used to fix EC gets stuck in low power + * mode when WRST# is asserted. + * + * By default, flash will go into deep power down mode automatically + * when EC is in low power mode. But we got an issue on IT83202BX that + * flash won't be able to wake up correctly when WRST# is asserted + * under this condition. + * This issue might cause cold reset failure so we fix it. + * + * NOTE: this fix will increase power number about 40uA in low power + * mode. + */ + if (mode == EC_PLL_DOZE) + IT83XX_SMFI_SMECCS &= ~IT83XX_SMFI_MASK_HOSTWA; + else + /* + * Don't send deep power down mode command to flash when EC in + * low power mode. + */ + IT83XX_SMFI_SMECCS |= IT83XX_SMFI_MASK_HOSTWA; +#endif /* * barrier: ensure low power mode setting is taken into control * register before standby instruction. diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index 88a1ee4960..b760adbc6b 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -35,6 +35,8 @@ #define CONFIG_FLASH_SIZE 0x00080000 /* Embedded flash is KGD */ #define IT83XX_CHIP_FLASH_IS_KGD +/* Don't let internal flash go into deep power down mode. */ +#define IT83XX_CHIP_FLASH_NO_DEEP_POWER_DOWN /* chip id is 3 bytes */ #define IT83XX_CHIP_ID_3BYTES /* diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index aeab504147..a6373ddc20 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1205,6 +1205,8 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4)) /* Shared Memory Flash Interface Bridge (SMFI) */ #define IT83XX_SMFI_BASE 0x00F01000 +#define IT83XX_SMFI_SMECCS REG8(IT83XX_SMFI_BASE+0x20) +#define IT83XX_SMFI_MASK_HOSTWA BIT(5) #define IT83XX_SMFI_HRAMWC REG8(IT83XX_SMFI_BASE+0x5A) #define IT83XX_SMFI_HRAMW0BA REG8(IT83XX_SMFI_BASE+0x5B) #define IT83XX_SMFI_HRAMW1BA REG8(IT83XX_SMFI_BASE+0x5C) |