Rename Cortex-M MMFS to CFSR

Taken as as 32-bit register, ARM call the register at 0xe000ed28 CFSR;
the Configurable Fault Status Register. MMFS is the low byte of this
value, so it's misleading to refer to the whole 32-bit value as MMFS;
instead call it CFSR to make it clear that the value we store
encompasses the MMFSR, BFSR and UFSR.

BUG=None
BRANCH=None
TEST=make buildall

Change-Id: Ifd62e0a6f27a2e6ddfa509b84c389d960347ff85
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2104807
Reviewed-by: Keith Short <keithshort@chromium.org>

5 files changed, 42 insertions, 58 deletions

diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index 48422902e0..d6d2c3b0b2 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -238,7 +238,7 @@ void system_set_rtc(uint32_t seconds)
  *
  * index     |       data
  * ==========|=============
- *   36      |       MMFS
+ *   36      |       CFSR
  *   40      |       HFSR
  *   44      |       BFAR
  *   48      |      LREG1
@@ -247,11 +247,11 @@ void system_set_rtc(uint32_t seconds)
  *   60      |     reserved
  *
  * Above registers are chosen to be saved in case of panic because:
- * 1. MMFS, HFSR and BFAR seem to provide more information about the fault.
+ * 1. CFSR, HFSR and BFAR seem to provide more information about the fault.
  * 2. LREG1, LREG3 and LREG4 store exception, reason and info in case of
  * software panic.
  */
-#define BKUP_MMFS		(BBRM_DATA_INDEX_PANIC_BKUP + 0)
+#define BKUP_CFSR		(BBRM_DATA_INDEX_PANIC_BKUP + 0)
 #define BKUP_HFSR		(BBRM_DATA_INDEX_PANIC_BKUP + 4)
 #define BKUP_BFAR		(BBRM_DATA_INDEX_PANIC_BKUP + 8)
 #define BKUP_LREG1		(BBRM_DATA_INDEX_PANIC_BKUP + 12)
@@ -267,7 +267,7 @@ void chip_panic_data_backup(void)
 	if (!d)
 		return;
 
-	bbram_data_write(BKUP_MMFS, d->cm.mmfs);
+	bbram_data_write(BKUP_CFSR, d->cm.cfsr);
 	bbram_data_write(BKUP_HFSR, d->cm.hfsr);
 	bbram_data_write(BKUP_BFAR, d->cm.dfsr);
 	bbram_data_write(BKUP_LREG1, d->cm.regs[1]);
@@ -281,7 +281,7 @@ static void chip_panic_data_restore(void)
 	struct panic_data *d = PANIC_DATA_PTR;
 
 	/* Ensure BBRAM is valid. */
-	if (!bbram_valid(BKUP_MMFS, 4))
+	if (!bbram_valid(BKUP_CFSR, 4))
 		return;
 
 	/* Ensure Panic data in BBRAM is valid. */
@@ -295,7 +295,7 @@ static void chip_panic_data_restore(void)
 	d->struct_version = 2;
 	d->arch = PANIC_ARCH_CORTEX_M;
 
-	d->cm.mmfs = bbram_data_read(BKUP_MMFS);
+	d->cm.cfsr = bbram_data_read(BKUP_CFSR);
 	d->cm.hfsr = bbram_data_read(BKUP_HFSR);
 	d->cm.dfsr = bbram_data_read(BKUP_BFAR);
 
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h
index 4cef402f85..6ff9f249be 100644
--- a/core/cortex-m/cpu.h
+++ b/core/cortex-m/cpu.h
@@ -39,15 +39,15 @@
 
 #define CPU_NVIC_CCR           CPUREG(0xe000ed14)
 #define CPU_NVIC_SHCSR         CPUREG(0xe000ed24)
-#define CPU_NVIC_MMFS          CPUREG(0xe000ed28)
+#define CPU_NVIC_CFSR          CPUREG(0xe000ed28)
 #define CPU_NVIC_HFSR          CPUREG(0xe000ed2c)
 #define CPU_NVIC_DFSR          CPUREG(0xe000ed30)
 #define CPU_NVIC_MFAR          CPUREG(0xe000ed34)
 #define CPU_NVIC_BFAR          CPUREG(0xe000ed38)
 
 enum {
-	CPU_NVIC_MMFS_BFARVALID		= BIT(15),
-	CPU_NVIC_MMFS_MFARVALID		= BIT(7),
+	CPU_NVIC_CFSR_BFARVALID		= BIT(15),
+	CPU_NVIC_CFSR_MFARVALID		= BIT(7),
 
 	CPU_NVIC_CCR_ICACHE		= BIT(17),
 	CPU_NVIC_CCR_DCACHE		= BIT(16),
diff --git a/core/cortex-m/panic.c b/core/cortex-m/panic.c
index 42582c8ca2..afdb3d858d 100644
--- a/core/cortex-m/panic.c
+++ b/core/cortex-m/panic.c
@@ -77,44 +77,28 @@ static int32_t is_frame_in_handler_stack(const uint32_t exc_return)
 }
 
 #ifdef CONFIG_DEBUG_EXCEPTIONS
-/* Names for each of the bits in the mmfs register, starting at bit 0 */
-static const char * const mmfs_name[32] = {
-	"Instruction access violation",
-	"Data access violation",
-	NULL,
-	"Unstack from exception violation",
-	"Stack from exception violation",
-	NULL,
-	NULL,
-	NULL,
-
-	"Instruction bus error",
-	"Precise data bus error",
-	"Imprecise data bus error",
-	"Unstack from exception bus fault",
-	"Stack from exception bus fault",
-	NULL,
-	NULL,
-	NULL,
-
-	"Undefined instructions",
-	"Invalid state",
-	"Invalid PC",
-	"No coprocessor",
-	NULL,
-	NULL,
-	NULL,
-	NULL,
-
-	"Unaligned",
-	"Divide by 0",
-	NULL,
-	NULL,
-
-	NULL,
-	NULL,
-	NULL,
-	NULL,
+/* Names for each of the bits in the cfs register, starting at bit 0 */
+static const char * const cfsr_name[32] = {
+	/* MMFSR */
+	[0] = "Instruction access violation",
+	[1] = "Data access violation",
+	[3] = "Unstack from exception violation",
+	[4] = "Stack from exception violation",
+
+	/* BFSR */
+	[8] = "Instruction bus error",
+	[9] = "Precise data bus error",
+	[10] = "Imprecise data bus error",
+	[11] = "Unstack from exception bus fault",
+	[12] = "Stack from exception bus fault",
+
+	/* UFSR */
+	[16] = "Undefined instructions",
+	[17] = "Invalid state",
+	[18] = "Invalid PC",
+	[19] = "No coprocessor",
+	[24] = "Unaligned",
+	[25] = "Divide by 0",
 };
 
 /* Names for the first 5 bits in the DFSR */
@@ -146,19 +130,19 @@ static void do_separate(int *count)
  *
  * A list of detected faults is shown, with no trailing newline.
  *
- * @param mmfs		Value of Memory Manage Fault Status
+ * @param cfsr		Value of Configurable Fault Status
  * @param hfsr		Value of Hard Fault Status
  * @param dfsr		Value of Debug Fault Status
  */
-static void show_fault(uint32_t mmfs, uint32_t hfsr, uint32_t dfsr)
+static void show_fault(uint32_t cfsr, uint32_t hfsr, uint32_t dfsr)
 {
 	unsigned int upto;
 	int count = 0;
 
 	for (upto = 0; upto < 32; upto++) {
-		if ((mmfs & BIT(upto)) && mmfs_name[upto]) {
+		if ((cfsr & BIT(upto)) && cfsr_name[upto]) {
 			do_separate(&count);
-			panic_puts(mmfs_name[upto]);
+			panic_puts(cfsr_name[upto]);
 		}
 	}
 
@@ -235,12 +219,12 @@ static uint32_t get_process_stack_position(const struct panic_data *pdata)
  */
 static void panic_show_extra(const struct panic_data *pdata)
 {
-	show_fault(pdata->cm.mmfs, pdata->cm.hfsr, pdata->cm.dfsr);
-	if (pdata->cm.mmfs & CPU_NVIC_MMFS_BFARVALID)
+	show_fault(pdata->cm.cfsr, pdata->cm.hfsr, pdata->cm.dfsr);
+	if (pdata->cm.cfsr & CPU_NVIC_CFSR_BFARVALID)
 		panic_printf(", bfar = %x", pdata->cm.bfar);
-	if (pdata->cm.mmfs & CPU_NVIC_MMFS_MFARVALID)
+	if (pdata->cm.cfsr & CPU_NVIC_CFSR_MFARVALID)
 		panic_printf(", mfar = %x", pdata->cm.mfar);
-	panic_printf("\nmmfs = %x, ", pdata->cm.mmfs);
+	panic_printf("\ncfsr = %x, ", pdata->cm.cfsr);
 	panic_printf("shcsr = %x, ", pdata->cm.shcsr);
 	panic_printf("hfsr = %x, ", pdata->cm.hfsr);
 	panic_printf("dfsr = %x\n", pdata->cm.dfsr);
@@ -330,7 +314,7 @@ void __keep report_panic(void)
 	}
 
 	/* Save extra information */
-	pdata->cm.mmfs = CPU_NVIC_MMFS;
+	pdata->cm.cfsr = CPU_NVIC_CFSR;
 	pdata->cm.bfar = CPU_NVIC_BFAR;
 	pdata->cm.mfar = CPU_NVIC_MFAR;
 	pdata->cm.shcsr = CPU_NVIC_SHCSR;
diff --git a/include/config.h b/include/config.h
index 22204bf717..ffe9b64eb2 100644
--- a/include/config.h
+++ b/include/config.h
@@ -1496,7 +1496,7 @@
  *	r8 :00000000 r9 :200013de r10:00000000 r11:00000000
  *	r12:00000000 sp :200009a0 lr :08002b85 pc :08003a8a
  *	Precise data bus error, Forced hard fault, Vector catch, bfar = 60000000
- *	mmfs = 00008200, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008
+ *	cfsr = 00008200, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008
  *
  * If this is not defined, only a register dump will be printed.
  *
diff --git a/include/panic.h b/include/panic.h
index 41b941d1ef..4708a9ff13 100644
--- a/include/panic.h
+++ b/include/panic.h
@@ -26,7 +26,7 @@ struct cortex_panic_data {
 				   */
 	uint32_t frame[8];        /* r0-r3, r12, lr, pc, xPSR */
 
-	uint32_t mmfs;
+	uint32_t cfsr;
 	uint32_t bfar;
 	uint32_t mfar;
 	uint32_t shcsr;