diff options
author | Sam Hurst <shurst@google.com> | 2020-08-03 13:06:42 -0700 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-08-05 18:41:25 +0000 |
commit | dede4e01ae4c877bb05d671087a6e85a29a0f902 (patch) | |
tree | 8aaaba7b7ce04c059ecd4df4de8a5609492065db | |
parent | e891cd5ebbb08c9101f1802c2dfcec755718d23f (diff) | |
download | chrome-ec-dede4e01ae4c877bb05d671087a6e85a29a0f902.tar.gz |
ec: change usage of dummy
Google is working to change its source code to use more inclusive
language. To that end, replace the term "dummy" with inclusive
alternatives.
BUG=b:162781382
BRANCH=None
TEST=make -j buildall
`grep -ir dummy *`
The only results are in "private/nordic_keyboard/sdk8.0.0"
which is not our code.
Signed-off-by: Sam Hurst <shurst@google.com>
Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
88 files changed, 232 insertions, 233 deletions
diff --git a/baseboard/dedede/variant_ec_it8320.c b/baseboard/dedede/variant_ec_it8320.c index 55c84cb2c0..71cb31203b 100644 --- a/baseboard/dedede/variant_ec_it8320.c +++ b/baseboard/dedede/variant_ec_it8320.c @@ -29,7 +29,7 @@ static void pp3300_a_pgood_low(void) vcmp_enable(VCMP_SNS_PP3300_HIGH, 1); /* - * Call power_signal_interrupt() with a dummy GPIO in order for the + * Call power_signal_interrupt() with a fake GPIO in order for the * chipset task to pick up the change in power sequencing signals. */ power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); @@ -46,7 +46,7 @@ static void pp3300_a_pgood_high(void) vcmp_enable(VCMP_SNS_PP3300_LOW, 1); /* - * Call power_signal_interrupt() with a dummy GPIO in order for the + * Call power_signal_interrupt() with a fake GPIO in order for the * chipset task to pick up the change in power sequencing signals. */ power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); diff --git a/baseboard/dedede/variant_ec_npcx796fc.c b/baseboard/dedede/variant_ec_npcx796fc.c index 966ffd30a1..ef8f5a79b2 100644 --- a/baseboard/dedede/variant_ec_npcx796fc.c +++ b/baseboard/dedede/variant_ec_npcx796fc.c @@ -36,7 +36,7 @@ void pp3300_a_pgood_high(void) npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1); /* - * Call power_signal_interrupt() with a dummy GPIO in order for the + * Call power_signal_interrupt() with a fake GPIO in order for the * chipset task to pick up the change in power sequencing signals. */ power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); @@ -52,7 +52,7 @@ void pp3300_a_pgood_low(void) npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1); /* - * Call power_signal_interrupt() with a dummy GPIO in order for the + * Call power_signal_interrupt() with a fake GPIO in order for the * chipset task to pick up the change in power sequencing signals. */ power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); diff --git a/board/host/board.c b/board/host/board.c index 2ee7413152..307ccac991 100644 --- a/board/host/board.c +++ b/board/host/board.c @@ -34,17 +34,17 @@ test_mockable enum battery_present battery_is_present(void) return BP_YES; } -test_mockable_static int dummy_temp_get_val(int idx, int *temp_ptr) +test_mockable_static int mock_temp_get_val(int idx, int *temp_ptr) { *temp_ptr = 0; return EC_SUCCESS; } const struct temp_sensor_t temp_sensors[] = { - {"CPU", TEMP_SENSOR_TYPE_CPU, dummy_temp_get_val, 0}, - {"Board", TEMP_SENSOR_TYPE_BOARD, dummy_temp_get_val, 1}, - {"Case", TEMP_SENSOR_TYPE_CASE, dummy_temp_get_val, 2}, - {"Battery", TEMP_SENSOR_TYPE_BOARD, dummy_temp_get_val, 3}, + {"CPU", TEMP_SENSOR_TYPE_CPU, mock_temp_get_val, 0}, + {"Board", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 1}, + {"Case", TEMP_SENSOR_TYPE_CASE, mock_temp_get_val, 2}, + {"Battery", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 3}, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); diff --git a/board/kukui/board.c b/board/kukui/board.c index 68edc00d3a..0f6107ceaa 100644 --- a/board/kukui/board.c +++ b/board/kukui/board.c @@ -263,7 +263,7 @@ int pd_snk_is_vbus_provided(int port) } #if defined(BOARD_KUKUI) || defined(BOARD_KODAMA) -/* dummy interrupt function for kukui */ +/* fake interrupt function for kukui */ void pogo_adc_interrupt(enum gpio_signal signal) { } diff --git a/board/nucleo-f072rb/board.c b/board/nucleo-f072rb/board.c index 48a51c7b02..66e8960ce7 100644 --- a/board/nucleo-f072rb/board.c +++ b/board/nucleo-f072rb/board.c @@ -18,7 +18,7 @@ void button_event(enum gpio_signal signal) #ifdef CTS_MODULE /* - * Dummy interrupt handler. It's supposed to be overwritten by each suite + * Mock interrupt handler. It's supposed to be overwritten by each suite * if needed. */ __attribute__((weak)) void cts_irq1(enum gpio_signal signal) {} diff --git a/board/reef_mchp/board.c b/board/reef_mchp/board.c index 04d1438799..621f6c484b 100644 --- a/board/reef_mchp/board.c +++ b/board/reef_mchp/board.c @@ -394,7 +394,7 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); * Upon receiving DRP low power idle command, PS8751 holds SCL and * SDA low for ~480us. It simultaneously releases both pins which is * defined as a bus error condition by I2C spec. No ACK received. - * TCPCI spec. states waking any TCPM requires sending any dummy + * TCPCI spec. states waking any TCPM requires sending any fake * I2C command which the TCPM will NACK. The I2C master MUST wait * a minimum of 5 ms after the NACK before sending another I2C * command. We observe the PD task and TCPCI state machines do not diff --git a/board/stm32l476g-eval/board.c b/board/stm32l476g-eval/board.c index 2ef46e8bc1..c7ebc2c6b8 100644 --- a/board/stm32l476g-eval/board.c +++ b/board/stm32l476g-eval/board.c @@ -11,7 +11,7 @@ #ifdef CTS_MODULE /* - * Dummy interrupt handler. It's supposed to be overwritten by each suite + * Mock interrupt handler. It's supposed to be overwritten by each suite * if needed. */ __attribute__((weak)) void cts_irq(enum gpio_signal signal) diff --git a/chip/host/clock.c b/chip/host/clock.c index 1bb3d56dfb..2c3c48661e 100644 --- a/chip/host/clock.c +++ b/chip/host/clock.c @@ -2,7 +2,7 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * - * Dummy clock driver for unit test. + * Mock clock driver for unit test. */ #include "clock.h" diff --git a/chip/host/i2c.c b/chip/host/i2c.c index f474c38ef1..8e6f086b4f 100644 --- a/chip/host/i2c.c +++ b/chip/host/i2c.c @@ -2,7 +2,7 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * - * Dummy I2C driver for unit test. + * Mock I2C driver for unit test. */ #include "hooks.h" diff --git a/chip/host/spi_master.c b/chip/host/spi_master.c index 83bde96163..1900e7b7a8 100644 --- a/chip/host/spi_master.c +++ b/chip/host/spi_master.c @@ -2,7 +2,7 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * - * Dummy Master SPI driver for unit test. + * Mock Master SPI driver for unit test. */ #include <stdint.h> diff --git a/chip/host/trng.c b/chip/host/trng.c index d90415df71..8407aa6ea1 100644 --- a/chip/host/trng.c +++ b/chip/host/trng.c @@ -3,7 +3,7 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * - * Dummy TRNG driver for unit test. + * Mock TRNG driver for unit test. * * Although a TRNG is designed to be anything but predictable, * this implementation strives to be as predictable and defined diff --git a/chip/ish/gpio.c b/chip/ish/gpio.c index 3d374f3cb8..6c7a27e1e7 100644 --- a/chip/ish/gpio.c +++ b/chip/ish/gpio.c @@ -21,7 +21,7 @@ test_mockable int gpio_get_level(enum gpio_signal signal) const struct gpio_info *g = gpio_list + signal; /* Unimplemented GPIOs shouldn't do anything */ - if (g->port == DUMMY_GPIO_BANK) + if (g->port == UNIMPLEMENTED_GPIO_BANK) return 0; return !!(ISH_GPIO_GPLR & g->mask); @@ -32,7 +32,7 @@ void gpio_set_level(enum gpio_signal signal, int value) const struct gpio_info *g = gpio_list + signal; /* Unimplemented GPIOs shouldn't do anything */ - if (g->port == DUMMY_GPIO_BANK) + if (g->port == UNIMPLEMENTED_GPIO_BANK) return; if (value) @@ -44,7 +44,7 @@ void gpio_set_level(enum gpio_signal signal, int value) void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) { /* Unimplemented GPIOs shouldn't do anything */ - if (port == DUMMY_GPIO_BANK) + if (port == UNIMPLEMENTED_GPIO_BANK) return; /* ISH does not support level-trigger interrupts; only edge. */ @@ -92,7 +92,7 @@ int gpio_enable_interrupt(enum gpio_signal signal) const struct gpio_info *g = gpio_list + signal; /* Unimplemented GPIOs shouldn't do anything */ - if (g->port == DUMMY_GPIO_BANK) + if (g->port == UNIMPLEMENTED_GPIO_BANK) return EC_SUCCESS; ISH_GPIO_GIMR |= g->mask; diff --git a/chip/ish/registers.h b/chip/ish/registers.h index 5942a89083..258abe33ef 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -13,7 +13,7 @@ #include "compile_time_macros.h" /* ISH GPIO has only one port */ -#define DUMMY_GPIO_BANK -1 +#define UNIMPLEMENTED_GPIO_BANK -1 /* * ISH3.0 has 3 controllers. Locking must occur by-controller (not by-port). diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 8a4fc99cf2..1d654295d2 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -854,7 +854,7 @@ static const struct gpio_reg_t gpio_group_to_reg[] = { }; BUILD_ASSERT(ARRAY_SIZE(gpio_group_to_reg) == (COUNT)); -#define DUMMY_GPIO_BANK GPIO_A +#define UNIMPLEMENTED_GPIO_BANK GPIO_A #define IT83XX_GPIO_DATA(port) \ REG8(gpio_group_to_reg[port].reg_gpdr) diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c index 82f64c65c8..4c70634bc2 100644 --- a/chip/it83xx/spi.c +++ b/chip/it83xx/spi.c @@ -265,7 +265,7 @@ void spi_slv_int_handler(void) * There is a limitation that Rx FIFO starts dropping * data when the CPU access the the FIFO. So we will * wait the data until Rx byte reach then to parse. - * The Rx FIFO to reach is dummy data generated by + * The Rx FIFO to reach is mock data generated by * generate clock that is not the bytes sent from * the host. */ @@ -291,7 +291,7 @@ static void spi_init(void) * bit6 : SPI pin function select (0b:Enable, 1b:Mask) */ IT83XX_GCTRL_MCCR3 |= IT83XX_GCTRL_SPISLVPFE; - /* Set dummy blcoked byte */ + /* Set unused blocked byte */ IT83XX_SPI_HPR2 = 0x00; /* Set FIFO data target count */ IT83XX_SPI_FTCB1R = (SPI_RX_MAX_FIFO_SIZE >> 8) & 0xff; diff --git a/chip/lm4/adc_chip.h b/chip/lm4/adc_chip.h index 8cf033b128..b43bec2da3 100644 --- a/chip/lm4/adc_chip.h +++ b/chip/lm4/adc_chip.h @@ -42,7 +42,7 @@ extern const struct adc_t adc_channels[]; /* Just plain id mapping for code readability */ #define LM4_AIN(x) (x) -/* Dummy value for "channel" in adc_t if we don't have an external channel. */ +/* Mock value for "channel" in adc_t if we don't have an external channel. */ #define LM4_AIN_NONE (-1) #endif /* __CROS_EC_ADC_CHIP_H */ diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c index 0c672bd63a..5b146ba32a 100644 --- a/chip/lm4/lpc.c +++ b/chip/lm4/lpc.c @@ -768,7 +768,7 @@ static void lpc_init(void) while (!(LM4_LPC_ST(LPC_CH_MEMMAP) & 0x10)) { /* Clear HW1ST */ LM4_LPC_ST(LPC_CH_MEMMAP) &= ~0x40; - /* Do a dummy slave write; this should cause SW1ST to be set */ + /* Do a slave write; this should cause SW1ST to be set */ *LPC_POOL_MEMMAP = *LPC_POOL_MEMMAP; } diff --git a/chip/lm4/registers.h b/chip/lm4/registers.h index da4741a344..0c59da19f6 100644 --- a/chip/lm4/registers.h +++ b/chip/lm4/registers.h @@ -489,7 +489,7 @@ enum clock_gate_offsets { #define GPIO_P LM4_GPIO_P #define GPIO_Q LM4_GPIO_Q -#define DUMMY_GPIO_BANK GPIO_A +#define UNIMPLEMENTED_GPIO_BANK GPIO_A /* Value to write to LM4_GPIO_LOCK to unlock writes */ #define LM4_GPIO_LOCK_UNLOCK 0x4c4f434b diff --git a/chip/lm4/spi.c b/chip/lm4/spi.c index 6df3d9e3ee..be988b78a0 100644 --- a/chip/lm4/spi.c +++ b/chip/lm4/spi.c @@ -65,12 +65,12 @@ int spi_transaction(const struct spi_device_t *spi_device, int totallen = txlen + rxlen; int txcount = 0, rxcount = 0; static struct mutex spi_mutex; - volatile uint32_t dummy __attribute__((unused)); + volatile uint32_t unused __attribute__((unused)); mutex_lock(&spi_mutex); /* Empty the receive FIFO */ while (LM4_SSI_SR(0) & LM4_SSI_SR_RNE) - dummy = LM4_SSI_DR(0); + unused = LM4_SSI_DR(0); /* Start transaction. Need to do this explicitly because the LM4 * SSI controller pulses its frame select every byte, and the EEPROM @@ -85,7 +85,7 @@ int spi_transaction(const struct spi_device_t *spi_device, if (rxcount < txlen) { /* Throw away bytes received while we were transmitting */ - dummy = LM4_SSI_DR(0); + unused = LM4_SSI_DR(0); } else *(rxdata++) = LM4_SSI_DR(0); rxcount++; @@ -96,7 +96,7 @@ int spi_transaction(const struct spi_device_t *spi_device, if (txcount < txlen) LM4_SSI_DR(0) = *(txdata++); else { - /* Clock out dummy byte so we can clock in the + /* Clock out unused byte so we can clock in the * response byte */ LM4_SSI_DR(0) = 0; } diff --git a/chip/lm4/watchdog.c b/chip/lm4/watchdog.c index 910cb87e03..50f122bf02 100644 --- a/chip/lm4/watchdog.c +++ b/chip/lm4/watchdog.c @@ -65,7 +65,7 @@ void watchdog_reload(void) if (status) { LM4_WATCHDOG_ICR(0) = status; /* That doesn't seem to unpend the watchdog interrupt (even if - * we do dummy writes to force the write to be committed), so + * we do writes to force the write to be committed), so * explicitly unpend the interrupt before re-enabling it. */ task_clear_pending_irq(LM4_IRQ_WATCHDOG); task_enable_irq(LM4_IRQ_WATCHDOG); diff --git a/chip/max32660/registers.h b/chip/max32660/registers.h index 8a2a072898..e444888fa0 100644 --- a/chip/max32660/registers.h +++ b/chip/max32660/registers.h @@ -142,7 +142,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ #define GPIO_3 PORT_3 /**< Port 3 Define*/ #define GPIO_4 PORT_4 /**< Port 4 Define*/ -#define DUMMY_GPIO_BANK GPIO_0 +#define UNIMPLEMENTED_GPIO_BANK GPIO_0 /******************************************************************************/ /* I2C */ diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c index ad8c47d38e..9fdb058898 100644 --- a/chip/mchp/clock.c +++ b/chip/mchp/clock.c @@ -94,7 +94,7 @@ int clock_get_freq(void) */ void clock_init(void) { - int __attribute__((unused)) dummy; + int __attribute__((unused)) unused; trace0(0, MEC, 0, "Clock Init"); @@ -117,8 +117,8 @@ void clock_init(void) #endif trace0(0, MEC, 0, "PLL OSC is Locked"); #ifndef LFW - dummy = shared_mem_size(); - trace11(0, MEC, 0, "Shared Memory size = 0x%08x", (uint32_t)dummy); + unused = shared_mem_size(); + trace11(0, MEC, 0, "Shared Memory size = 0x%08x", (uint32_t)unused); #endif } diff --git a/chip/mchp/config_chip.h b/chip/mchp/config_chip.h index 7a0008958c..747a10a8b8 100644 --- a/chip/mchp/config_chip.h +++ b/chip/mchp/config_chip.h @@ -44,7 +44,7 @@ * MCHP I2C controller is master-slave capable and requires * a slave address be programmed even if used as master only. * Each I2C controller can respond to two slave address. - * Define dummy slave addresses that aren't used on the I2C port(s) + * Define fake slave addresses that aren't used on the I2C port(s) * connected to each controller. */ #define CONFIG_MCHP_I2C0_SLAVE_ADDRS 0xE3E1 diff --git a/chip/mchp/dma.c b/chip/mchp/dma.c index 6c9ed8dd47..982dfa8122 100644 --- a/chip/mchp/dma.c +++ b/chip/mchp/dma.c @@ -43,7 +43,7 @@ void dma_disable(enum dma_channel channel) void dma_disable_all(void) { uint16_t ch; - uint32_t dummy = 0; + uint32_t unused = 0; for (ch = 0; ch < MCHP_DMAC_COUNT; ch++) { /* Abort any current transfer. */ @@ -55,7 +55,7 @@ void dma_disable_all(void) /* Soft-reset the block. */ MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_SRST; - dummy += MCHP_DMA_MAIN_CTRL; + unused += MCHP_DMA_MAIN_CTRL; MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_ACT; } diff --git a/chip/mchp/gpspi.c b/chip/mchp/gpspi.c index f8b556d389..4edf57ee11 100644 --- a/chip/mchp/gpspi.c +++ b/chip/mchp/gpspi.c @@ -56,14 +56,14 @@ static int gpspi_wait_byte(const int ctrl) /* NOTE: auto-read must be disabled before calling this routine! */ static void gpspi_rx_fifo_clean(const int ctrl) { - uint8_t dummy = 0; + uint8_t unused = 0; /* If ACTIVE and/or RXFF then clean it */ if ((MCHP_SPI_SR(ctrl) & 0x4) == 0x4) - dummy += MCHP_SPI_RD(ctrl); + unused += MCHP_SPI_RD(ctrl); if ((MCHP_SPI_SR(ctrl) & 0x2) == 0x2) - dummy += MCHP_SPI_RD(ctrl); + unused += MCHP_SPI_RD(ctrl); } /* * NOTE: auto-read must be disabled before calling this routine! @@ -73,7 +73,7 @@ static int gpspi_tx(const int ctrl, const uint8_t *txdata, int txlen) { int i; int ret; - uint8_t dummy = 0; + uint8_t unused = 0; gpspi_rx_fifo_clean(ctrl); @@ -83,7 +83,7 @@ static int gpspi_tx(const int ctrl, const uint8_t *txdata, int txlen) ret = gpspi_wait_byte(ctrl); if (ret != EC_SUCCESS) break; - dummy += MCHP_SPI_RD(ctrl); + unused += MCHP_SPI_RD(ctrl); } return ret; diff --git a/chip/mchp/i2c.c b/chip/mchp/i2c.c index ab2c75c754..da7136a6b2 100644 --- a/chip/mchp/i2c.c +++ b/chip/mchp/i2c.c @@ -454,7 +454,7 @@ static int wait_byte_done(int controller, uint8_t mask, uint8_t expected) * Switch port by reset and reconfigure to handle cases where * the slave on current port is driving line(s) low. * NOTE: I2C hardware reset only requires one AHB clock, back to back - * writes is OK but we added a dummy write as insurance. + * writes is OK but we added an extra write as insurance. */ static void select_port(int port, int controller) { @@ -465,7 +465,7 @@ static void select_port(int port, int controller) return; MCHP_I2C_CONFIG(controller) |= BIT(9); - MCHP_EC_ID_RO = 0; /* dummy write to read-only as delay */ + MCHP_EC_ID_RO = 0; /* extra write to read-only as delay */ MCHP_I2C_CONFIG(controller) &= ~BIT(9); configure_controller(controller, port_sel, i2c_ports[port].kbps); } @@ -651,7 +651,7 @@ static int i2c_mrx_start(int ctrl) return rv; } /* if STOP requested and last 1 or 2 bytes prepare controller - * to NACK last byte. Do this before read of dummy data so + * to NACK last byte. Do this before read of extra data so * controller is setup to NACK last byte. */ cdata[ctrl].flags |= (1ul << 8); diff --git a/chip/mchp/qmspi.c b/chip/mchp/qmspi.c index 1a5f9576b8..72eaa91d37 100644 --- a/chip/mchp/qmspi.c +++ b/chip/mchp/qmspi.c @@ -436,7 +436,7 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device, * aligned >= 4 bytes and the number of bytes is a multiple of 4. * NOTE on SPI flash commands: * This routine does NOT handle SPI flash commands requiring - * dummy clocks or special mode bytes. Dummy clocks and special mode + * extra clocks or special mode bytes. Extra clocks and special mode * bytes require additional descriptors. For example the flash read * dual command (0x3B): * 1. First descriptor transmits 4 bytes (opcode + 24-bit address) on @@ -444,7 +444,7 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device, * 2. Second descriptor set for 2 IO pins, 2 bytes, TX disabled. When * this descriptor is executed QMSPI will tri-state IO0 & IO1 and * output 8 clocks (dual mode 4 clocks per byte). The SPI flash may - * turn on its output drivers on the first dummy clock. + * turn on its output drivers on the first clock. * 3. Third descriptor set for 2 IO pins, read data using DMA. Unit * size and DMA unit size based on number of bytes to read and * alignment of destination buffer. @@ -455,14 +455,14 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device, * the SPI flash that changes the default 24-bit address command to * require a 32-bit address. * 0x03 is 1-1-1 - * 0x3B is 1-1-2 with 8 dummy clocks - * 0x6B is 1-1-4 with 8 dummy clocks - * 0xBB is 1-2-2 with 4 dummy clocks + * 0x3B is 1-1-2 with 8 clocks + * 0x6B is 1-1-4 with 8 clocks + * 0xBB is 1-2-2 with 4 clocks * Number of IO pins for command * Number of IO pins for address * Number of IO pins for data * Number of bit/bytes for address (3 or 4) - * Number of dummy clocks after address phase + * Number of clocks after address phase */ #ifdef CONFIG_MCHP_QMSPI_TX_DMA int qmspi_transaction_async(const struct spi_device_t *spi_device, @@ -671,7 +671,7 @@ int qmspi_transaction_flush(const struct spi_device_t *spi_device) */ int qmspi_enable(int hw_port, int enable) { - uint8_t dummy __attribute__((unused)) = 0; + uint8_t unused __attribute__((unused)) = 0; trace2(0, QMSPI, 0, "qmspi_enable: port = %d enable = %d", hw_port, enable); @@ -684,13 +684,13 @@ int qmspi_enable(int hw_port, int enable) if (enable) { MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_QMSPI); MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET; - dummy = MCHP_QMSPI0_MODE_ACT_SRST; + unused = MCHP_QMSPI0_MODE_ACT_SRST; MCHP_QMSPI0_MODE = (MCHP_QMSPI_M_ACTIVATE + MCHP_QMSPI_M_SPI_MODE0 + MCHP_QMSPI_M_CLKDIV_12M); } else { MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET; - dummy = MCHP_QMSPI0_MODE_ACT_SRST; + unused = MCHP_QMSPI0_MODE_ACT_SRST; MCHP_QMSPI0_MODE_ACT_SRST = 0; MCHP_PCR_SLP_EN_DEV(MCHP_PCR_QMSPI); } diff --git a/chip/mchp/registers.h b/chip/mchp/registers.h index f7ef36e68c..145e61257d 100644 --- a/chip/mchp/registers.h +++ b/chip/mchp/registers.h @@ -594,7 +594,7 @@ /* MCHP implements 6 GPIO ports */ #define MCHP_GPIO_MAX_PORT (7) -#define DUMMY_GPIO_BANK 0 +#define UNIMPLEMENTED_GPIO_BANK 0 /* * MEC1701 documentation GPIO numbers are octal, each control diff --git a/chip/mchp/util/pack_ec.py b/chip/mchp/util/pack_ec.py index 22a147ed95..4917deee5d 100755 --- a/chip/mchp/util/pack_ec.py +++ b/chip/mchp/util/pack_ec.py @@ -31,10 +31,10 @@ SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b] CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d] -def dummy_print(*args, **kwargs): +def mock_print(*args, **kwargs): pass -debug_print = dummy_print +debug_print = mock_print def Crc8(crc, data): """Update CRC8 value.""" diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c index fe72b870ef..69344d8390 100644 --- a/chip/mec1322/i2c.c +++ b/chip/mec1322/i2c.c @@ -348,7 +348,7 @@ int chip_i2c_xfer(const int port, cdata[controller].transaction_state = I2C_TRANSACTION_OPEN; - /* Skip over the dummy byte */ + /* Skip over the unused byte */ skip = 1; in_size++; } @@ -388,7 +388,7 @@ int chip_i2c_xfer(const int port, /* * We need to know our stop point two bytes in * advance. If we don't know soon enough, we need - * to do an extra dummy read (to last_addr + 1) to + * to do an extra read (to last_addr + 1) to * issue the stop. */ push_in_buf(&in, MEC1322_I2C_DATA(controller), diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index 69fe3b856c..020cd0e23e 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -454,9 +454,9 @@ void lpc_keyboard_put_char(uint8_t chr, int send_irq) void lpc_keyboard_clear_buffer(void) { - volatile char dummy __attribute__((unused)); + volatile char unused __attribute__((unused)); - dummy = MEC1322_8042_OBF_CLR; + unused = MEC1322_8042_OBF_CLR; } void lpc_keyboard_resume_irq(void) diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h index 7e5bbc7cea..c59b590ef8 100644 --- a/chip/mec1322/registers.h +++ b/chip/mec1322/registers.h @@ -118,7 +118,7 @@ static inline uintptr_t gpio_port_base(int port_id) } #define MEC1322_GPIO_CTL(port, id) REG32(gpio_port_base(port) + (id << 2)) -#define DUMMY_GPIO_BANK 0 +#define UNIMPLEMENTED_GPIO_BANK 0 /* Timer */ diff --git a/chip/mec1322/spi.c b/chip/mec1322/spi.c index 834fbd10b1..ba58bfb0bd 100644 --- a/chip/mec1322/spi.c +++ b/chip/mec1322/spi.c @@ -60,14 +60,14 @@ static int spi_tx(const int port, const uint8_t *txdata, int txlen) { int i; int ret = EC_SUCCESS; - uint8_t dummy __attribute__((unused)) = 0; + uint8_t unused __attribute__((unused)) = 0; for (i = 0; i < txlen; ++i) { MEC1322_SPI_TD(port) = txdata[i]; ret = wait_byte(port); if (ret != EC_SUCCESS) return ret; - dummy = MEC1322_SPI_RD(port); + unused = MEC1322_SPI_RD(port); } return ret; @@ -103,7 +103,7 @@ int spi_transaction_flush(const struct spi_device_t *spi_device) { int port = spi_device->port; int ret = dma_wait(SPI_DMA_CHANNEL(port)); - uint8_t dummy __attribute__((unused)) = 0; + uint8_t unused __attribute__((unused)) = 0; timestamp_t deadline; @@ -121,7 +121,7 @@ int spi_transaction_flush(const struct spi_device_t *spi_device) dma_disable(SPI_DMA_CHANNEL(port)); dma_clear_isr(SPI_DMA_CHANNEL(port)); if (MEC1322_SPI_SR(port) & 0x2) - dummy = MEC1322_SPI_RD(port); + unused = MEC1322_SPI_RD(port); gpio_set_level(spi_device->gpio_cs, 1); diff --git a/chip/mt8192_scp/ipi_chip.h b/chip/mt8192_scp/ipi_chip.h index 13345fc6e2..8cc3376880 100644 --- a/chip/mt8192_scp/ipi_chip.h +++ b/chip/mt8192_scp/ipi_chip.h @@ -79,8 +79,8 @@ extern int *const ipi_wakeup_table[]; */ #define DECLARE_IPI(_id, handler, is_wakeup_src) \ struct ipi_num_check##_id { \ - int dummy1[_id < IPI_COUNT ? 1 : -1]; \ - int dummy2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \ + int tmp1[_id < IPI_COUNT ? 1 : -1]; \ + int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \ }; \ void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \ { \ diff --git a/chip/mt8192_scp/registers.h b/chip/mt8192_scp/registers.h index dbf0aed64d..b5c658f534 100644 --- a/chip/mt8192_scp/registers.h +++ b/chip/mt8192_scp/registers.h @@ -11,7 +11,7 @@ #include "common.h" #include "compile_time_macros.h" -#define DUMMY_GPIO_BANK 0 +#define UNIMPLEMENTED_GPIO_BANK 0 #define SCP_REG_BASE 0x70000000 diff --git a/chip/mt_scp/ipi_chip.h b/chip/mt_scp/ipi_chip.h index 6b9580e112..867a84c9f8 100644 --- a/chip/mt_scp/ipi_chip.h +++ b/chip/mt_scp/ipi_chip.h @@ -104,8 +104,8 @@ extern int *ipi_wakeup_table[]; */ #define DECLARE_IPI(_id, handler, is_wakeup_src) \ struct ipi_num_check##_id { \ - int dummy1[_id < IPI_COUNT ? 1 : -1]; \ - int dummy2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \ + int tmp1[_id < IPI_COUNT ? 1 : -1]; \ + int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \ }; \ void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \ { \ diff --git a/chip/mt_scp/memmap.c b/chip/mt_scp/memmap.c index 5926ae791e..6d8f2b0c87 100644 --- a/chip/mt_scp/memmap.c +++ b/chip/mt_scp/memmap.c @@ -70,7 +70,7 @@ void cpu_invalidate_dcache(void) SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK; SCP_CACHE_OP(CACHE_DCACHE) |= OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN; - /* Dummy read is necessary to confirm the invalidation finish. */ + /* Read is necessary to confirm the invalidation finish. */ REG32(CACHE_TRANS_SCP_CACHE_ADDR); asm volatile("dsb;"); } @@ -85,7 +85,7 @@ void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length) SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK; SCP_CACHE_OP(CACHE_DCACHE) |= OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN; - /* Dummy read necessary to confirm the invalidation finish. */ + /* Read necessary to confirm the invalidation finish. */ REG32(addr); } asm volatile("dsb;"); @@ -99,7 +99,7 @@ void cpu_clean_invalidate_dcache(void) SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK; SCP_CACHE_OP(CACHE_DCACHE) |= OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN; - /* Dummy read necessary to confirm the invalidation finish. */ + /* Read necessary to confirm the invalidation finish. */ REG32(CACHE_TRANS_SCP_CACHE_ADDR); asm volatile("dsb;"); } @@ -117,7 +117,7 @@ void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length) SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK; SCP_CACHE_OP(CACHE_DCACHE) |= OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN; - /* Dummy read necessary to confirm the invalidation finish. */ + /* Read necessary to confirm the invalidation finish. */ REG32(addr); } asm volatile("dsb;"); diff --git a/chip/mt_scp/registers.h b/chip/mt_scp/registers.h index bce632c6b7..21270b452d 100644 --- a/chip/mt_scp/registers.h +++ b/chip/mt_scp/registers.h @@ -573,7 +573,7 @@ */ #define AP_GPIO_MODE(n) REG32(AP_GPIO_BASE + 0x300 + ((n) << 4)) #define AP_GPIO_TRAP REG32(AP_GPIO_BASE + 0x6B0) -#define AP_GPIO_DUMMY REG32(AP_GPIO_BASE + 0x6C0) +#define AP_GPIO_UNIMPLEMENTED REG32(AP_GPIO_BASE + 0x6C0) #define AP_GPIO_DBG REG32(AP_GPIO_BASE + 0x6D0) #define AP_GPIO_BANK REG32(AP_GPIO_BASE + 0x6E0) /* AP_GPIO_SEC, n in [0..5] */ @@ -610,7 +610,7 @@ #define OSC_MOD_MASK (0x03 << 0) #define OSC_DIV2_EN BIT(2) -#define DUMMY_GPIO_BANK 0 +#define UNIMPLEMENTED_GPIO_BANK 0 #ifndef __ASSEMBLER__ diff --git a/chip/npcx/i2c.c b/chip/npcx/i2c.c index 17b183bc71..b4879081e8 100644 --- a/chip/npcx/i2c.c +++ b/chip/npcx/i2c.c @@ -99,7 +99,7 @@ enum smb_oper_state_t { SMB_MASTER_START, SMB_WRITE_OPER, SMB_READ_OPER, - SMB_DUMMY_READ_OPER, + SMB_FAKE_READ_OPER, SMB_REPEAT_START, SMB_WRITE_SUSPEND, SMB_READ_SUSPEND, @@ -348,7 +348,7 @@ enum smb_error i2c_master_transaction(int controller) } else if (p_status->oper_state == SMB_READ_SUSPEND) { if (!IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { /* - * Do dummy read if read length is 1 and I2C_XFER_STOP + * Do extra read if read length is 1 and I2C_XFER_STOP * is set simultaneously. */ if (p_status->sz_rxbuf == 1 && @@ -356,13 +356,13 @@ enum smb_error i2c_master_transaction(int controller) /* * Since SCL is released after reading last * byte from previous transaction, adding a - * dummy byte for next transaction which let + * extra byte for next transaction which let * ec sets NACK bit in time is necessary. * Or i2c master cannot generate STOP * when the last byte is ACK during receiving. */ p_status->sz_rxbuf++; - p_status->oper_state = SMB_DUMMY_READ_OPER; + p_status->oper_state = SMB_FAKE_READ_OPER; } else /* * Need to read the other bytes from @@ -475,7 +475,7 @@ void i2c_done(int controller) NPCX_SMBFIF_CTS(controller) = BIT(NPCX_SMBFIF_CTS_RXF_TXE); - /* Clear SDAST by writing dummy byte */ + /* Clear SDAST by writing mock byte */ I2C_WRITE_BYTE(controller, 0xFF); } @@ -536,8 +536,8 @@ static void i2c_handle_receive(int controller) I2C_READ_BYTE(controller, data); CPRINTS("-R(%02x)", data); - /* Read to buf. Skip last byte if meet SMB_DUMMY_READ_OPER */ - if (p_status->oper_state == SMB_DUMMY_READ_OPER && + /* Read to buf. Skip last byte if meet SMB_FAKE_READ_OPER */ + if (p_status->oper_state == SMB_FAKE_READ_OPER && p_status->idx_buf == (p_status->sz_rxbuf - 1)) p_status->idx_buf++; else @@ -735,7 +735,7 @@ static void i2c_handle_sda_irq(int controller) } /* 3 Handle master read operation (read or after a write operation) */ else if (p_status->oper_state == SMB_READ_OPER || - p_status->oper_state == SMB_DUMMY_READ_OPER) { + p_status->oper_state == SMB_FAKE_READ_OPER) { if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) i2c_fifo_handle_receive(controller); else @@ -755,7 +755,7 @@ void i2c_master_int_handler (int controller) CPUTS("-SP"); /* Clear BER Bit */ SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_BER); - /* Mask sure slave doesn't hold bus by dummy reading */ + /* Make sure slave doesn't hold bus by reading */ I2C_READ_BYTE(controller, data); /* Set error code */ diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 8e94f1f125..5b173493d6 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -509,7 +509,7 @@ enum { #define GPIO_D GPIO_PORT_D #define GPIO_E GPIO_PORT_E #define GPIO_F GPIO_PORT_F -#define DUMMY_GPIO_BANK GPIO_PORT_0 +#define UNIMPLEMENTED_GPIO_BANK GPIO_PORT_0 /******************************************************************************/ /* MSWC Registers */ diff --git a/chip/npcx/spi.c b/chip/npcx/spi.c index 3be5f16410..6ac8fe1b9e 100644 --- a/chip/npcx/spi.c +++ b/chip/npcx/spi.c @@ -35,9 +35,9 @@ */ static void clear_databuf(void) { - volatile uint8_t dummy __attribute__((unused)); + volatile uint8_t unused __attribute__((unused)); while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF)) - dummy = NPCX_SPI_DATA; + unused = NPCX_SPI_DATA; } /** @@ -156,7 +156,7 @@ int spi_transaction(const struct spi_device_t *spi_device, /* Waiting till reading is finished */ while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF)) ; - /* Reading the (dummy) data */ + /* Reading the (unused) data */ clear_databuf(); } CPRINTS("write end"); @@ -165,7 +165,7 @@ int spi_transaction(const struct spi_device_t *spi_device, /* Making sure we can write */ while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY)) ; - /* Write the (dummy) data */ + /* Write the (unused) data */ NPCX_SPI_DATA = 0; /* Wait till reading is finished */ while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF)) diff --git a/chip/nrf51/registers.h b/chip/nrf51/registers.h index d41e80c76c..daf014df72 100644 --- a/chip/nrf51/registers.h +++ b/chip/nrf51/registers.h @@ -665,7 +665,7 @@ #define NRF51_PIN_CNF_SENSE_HIGH (2<<16) #define NRF51_PIN_CNF_SENSE_LOW (3<<16) -#define DUMMY_GPIO_BANK GPIO_0 /* for UNIMPLEMENTED() macro */ +#define UNIMPLEMENTED_GPIO_BANK GPIO_0 /* for UNIMPLEMENTED() macro */ #define NRF51_PPI_BASE 0x4001F000 #define NRF51_PPI_CHEN REG32(NRF51_PPI_BASE + 0x500) diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c index 180dc05c3b..fb3e4604a8 100644 --- a/chip/stm32/adc-stm32f3.c +++ b/chip/stm32/adc-stm32f3.c @@ -231,7 +231,7 @@ static void adc_init(void) /* * ADC clock is divided with respect to AHB, so no delay needed - * here. If ADC clock is the same as AHB, a dummy read on ADC + * here. If ADC clock is the same as AHB, a read on ADC * register is needed here. */ diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index bea8a7b829..8cfbaef111 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -388,14 +388,14 @@ int clock_get_freq(void) void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) { - volatile uint32_t dummy __attribute__((unused)); + volatile uint32_t unused __attribute__((unused)); if (bus == BUS_AHB) { while (cycles--) - dummy = STM32_DMA1_REGS->isr; + unused = STM32_DMA1_REGS->isr; } else { /* APB */ while (cycles--) - dummy = STM32_USART_BRR(STM32_USART1_BASE); + unused = STM32_USART_BRR(STM32_USART1_BASE); } } diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c index 709ac42981..7b83b8507e 100644 --- a/chip/stm32/clock-stm32f4.c +++ b/chip/stm32/clock-stm32f4.c @@ -174,14 +174,14 @@ int clock_get_freq(void) void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) { - volatile uint32_t dummy __attribute__((unused)); + volatile uint32_t unused __attribute__((unused)); if (bus == BUS_AHB) { while (cycles--) - dummy = STM32_DMA_GET_ISR(0); + unused = STM32_DMA_GET_ISR(0); } else { /* APB */ while (cycles--) - dummy = STM32_USART_BRR(STM32_USART1_BASE); + unused = STM32_USART_BRR(STM32_USART1_BASE); } } diff --git a/chip/stm32/clock-stm32g4.c b/chip/stm32/clock-stm32g4.c index 488adacf59..4a91e1ad42 100644 --- a/chip/stm32/clock-stm32g4.c +++ b/chip/stm32/clock-stm32g4.c @@ -229,14 +229,14 @@ int clock_get_freq(void) void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) { - volatile uint32_t dummy __attribute__((unused)); + volatile uint32_t unused __attribute__((unused)); if (bus == BUS_AHB) { while (cycles--) - dummy = STM32_DMA1_REGS->isr; + unused = STM32_DMA1_REGS->isr; } else { /* APB */ while (cycles--) - dummy = STM32_USART_BRR(STM32_USART1_BASE); + unused = STM32_USART_BRR(STM32_USART1_BASE); } } diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c index bfc56f81df..ba233dbd76 100644 --- a/chip/stm32/clock-stm32h7.c +++ b/chip/stm32/clock-stm32h7.c @@ -104,14 +104,14 @@ int clock_get_timer_freq(void) void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) { - volatile uint32_t dummy __attribute__((unused)); + volatile uint32_t unused __attribute__((unused)); if (bus == BUS_AHB) { while (cycles--) - dummy = STM32_GPIO_IDR(GPIO_A); + unused = STM32_GPIO_IDR(GPIO_A); } else { /* APB */ while (cycles--) - dummy = STM32_USART_BRR(STM32_USART1_BASE); + unused = STM32_USART_BRR(STM32_USART1_BASE); } } diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c index 96acfc85ad..a4e9dd7cdf 100644 --- a/chip/stm32/clock-stm32l.c +++ b/chip/stm32/clock-stm32l.c @@ -57,14 +57,14 @@ int clock_get_timer_freq(void) void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) { - volatile uint32_t dummy __attribute__((unused)); + volatile uint32_t unused __attribute__((unused)); if (bus == BUS_AHB) { while (cycles--) - dummy = STM32_DMA1_REGS->isr; + unused = STM32_DMA1_REGS->isr; } else { /* APB */ while (cycles--) - dummy = STM32_USART_BRR(STM32_USART1_BASE); + unused = STM32_USART_BRR(STM32_USART1_BASE); } } diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c index b180177d0b..1bba787779 100644 --- a/chip/stm32/clock-stm32l4.c +++ b/chip/stm32/clock-stm32l4.c @@ -44,14 +44,14 @@ int clock_get_timer_freq(void) void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) { - volatile uint32_t dummy __attribute__((unused)); + volatile uint32_t unused __attribute__((unused)); if (bus == BUS_AHB) { while (cycles--) - dummy = STM32_DMA1_REGS->isr; + unused = STM32_DMA1_REGS->isr; } else { /* APB */ while (cycles--) - dummy = STM32_USART_BRR(STM32_USART1_BASE); + unused = STM32_USART_BRR(STM32_USART1_BASE); } } diff --git a/chip/stm32/i2c-stm32f4.c b/chip/stm32/i2c-stm32f4.c index 8c08395edd..515aed20eb 100644 --- a/chip/stm32/i2c-stm32f4.c +++ b/chip/stm32/i2c-stm32f4.c @@ -860,7 +860,7 @@ static void i2c_event_handler(int port) static int rx_pending, buf_idx; static uint16_t addr_8bit; - volatile uint32_t dummy __attribute__((unused)); + volatile uint32_t unused __attribute__((unused)); i2c_cr1 = STM32_I2C_CR1(port); i2c_sr2 = STM32_I2C_SR2(port); @@ -903,8 +903,8 @@ static void i2c_event_handler(int port) /* Enable buffer interrupt to start receive/response */ STM32_I2C_CR2(port) |= STM32_I2C_CR2_ITBUFEN; /* Clear ADDR bit */ - dummy = STM32_I2C_SR1(port); - dummy = STM32_I2C_SR2(port); + unused = STM32_I2C_SR1(port); + unused = STM32_I2C_SR2(port); /* Inhibit stop mode when addressed until STOPF flag is set */ disable_sleep(SLEEP_MASK_I2C_SLAVE); } @@ -964,7 +964,7 @@ static void i2c_event_handler(int port) /* Clear AF */ STM32_I2C_SR1(port) &= ~STM32_I2C_SR1_AF; /* Clear STOPF: read SR1 and write CR1 */ - dummy = STM32_I2C_SR1(port); + unused = STM32_I2C_SR1(port); STM32_I2C_CR1(port) = i2c_cr1 | STM32_I2C_CR1_PE; /* No longer inhibit deep sleep after stop condition */ diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index ea6b2db84a..574921c63e 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -183,7 +183,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define GPIO_J STM32_GPIOJ_BASE #define GPIO_K STM32_GPIOK_BASE -#define DUMMY_GPIO_BANK GPIO_A +#define UNIMPLEMENTED_GPIO_BANK GPIO_A /* --- I2C --- */ diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c index 21857837c2..3dbbbc4fa9 100644 --- a/chip/stm32/spi.c +++ b/chip/stm32/spi.c @@ -308,7 +308,7 @@ static void tx_status(uint8_t byte) static void setup_for_transaction(void) { stm32_spi_regs_t *spi __attribute__((unused)) = STM32_SPI1_REGS; - volatile uint8_t dummy __attribute__((unused)); + volatile uint8_t unused __attribute__((unused)); /* clear this as soon as possible */ setup_transaction_later = 0; @@ -325,15 +325,15 @@ static void setup_for_transaction(void) dma_disable(STM32_DMAC_SPI1_TX); /* - * Read dummy bytes in case there are some pending; this prevents the + * Read unused bytes in case there are some pending; this prevents the * receive DMA from getting that byte right when we start it. */ - dummy = SPI_RXDR; + unused = SPI_RXDR; #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4) /* 4 Bytes makes sure the RX FIFO on the F0 is empty as well. */ - dummy = spi->dr; - dummy = spi->dr; - dummy = spi->dr; + unused = spi->dr; + unused = spi->dr; + unused = spi->dr; #endif /* Start DMA */ @@ -523,7 +523,7 @@ void spi_event(enum gpio_signal signal) /* * Check how big the packet should be. We can't just wait to * see how much data the host sends, because it will keep - * sending dummy data until we respond. + * sending extra data until we respond. */ pkt_size = host_request_expected_size(r); if (pkt_size == 0 || pkt_size > sizeof(in_msg)) diff --git a/chip/stm32/spi_master.c b/chip/stm32/spi_master.c index 4b48f8ea80..c2d36bb4d9 100644 --- a/chip/stm32/spi_master.c +++ b/chip/stm32/spi_master.c @@ -117,11 +117,11 @@ static int spi_rx_done(stm32_spi_regs_t *spi) /* Read until RX FIFO is empty (i.e. RX done) */ static int spi_clear_rx_fifo(stm32_spi_regs_t *spi) { - uint8_t dummy __attribute__((unused)); + uint8_t unused __attribute__((unused)); uint32_t start = __hw_clock_source_read(), delta; while (!spi_rx_done(spi)) { - dummy = spi->dr; /* Read one byte from FIFO */ + unused = spi->dr; /* Read one byte from FIFO */ delta = __hw_clock_source_read() - start; if (delta >= SPI_TRANSACTION_TIMEOUT_USEC) return EC_ERROR_TIMEOUT; diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c index eff3ca0181..48d5335c53 100644 --- a/chip/stm32/trng.c +++ b/chip/stm32/trng.c @@ -21,7 +21,7 @@ uint32_t rand(void) /* Wait for a valid random number */ while (!(STM32_RNG_SR & STM32_RNG_SR_DRDY) && --tries) ; - /* we cannot afford to feed the caller with a dummy number */ + /* we cannot afford to feed the caller with an arbitrary number */ if (!tries) software_panic(PANIC_SW_BAD_RNG, task_get_current()); /* Finally the 32-bit of entropy */ diff --git a/common/build.mk b/common/build.mk index de4d9def39..8a2cd33cbd 100644 --- a/common/build.mk +++ b/common/build.mk @@ -208,11 +208,11 @@ endif else -# generate a dummy bootblock file -BOOTBLOCK := $(out)/.dummy-bootblock +# generate a fake bootblock file +BOOTBLOCK := $(out)/.fake-bootblock -.PHONY: $(out)/.dummy-bootblock -$(out)/.dummy-bootblock: +.PHONY: $(out)/.fake-bootblock +$(out)/.fake-bootblock: @dd if=/dev/zero of=$@ bs=1 count=$(DEFAULT_BOOTBLOCK_SIZE) status=none endif # BOOTBLOCK diff --git a/common/host_command_master.c b/common/host_command_master.c index 5f707eac1a..d51c8cdc15 100644 --- a/common/host_command_master.c +++ b/common/host_command_master.c @@ -95,7 +95,7 @@ static int pd_host_command_internal(int command, int version, resp_len = resp_buf[1]; if (resp_len > (insize + sizeof(rs))) { - /* Do a dummy read to generate stop condition */ + /* Do a read to generate stop condition */ i2c_xfer_unlocked(I2C_PORT_PD_MCU, CONFIG_USB_PD_I2C_SLAVE_ADDR_FLAGS, 0, 0, &resp_buf[2], 1, I2C_XFER_STOP); diff --git a/common/spi_nor.c b/common/spi_nor.c index 98a9a01af8..4fda9f41e1 100644 --- a/common/spi_nor.c +++ b/common/spi_nor.c @@ -228,7 +228,7 @@ static int spi_nor_read_sfdp_dword( sfdp_cmd[1] = (sfdp_offset & 0xFF0000) >> 16; sfdp_cmd[2] = (sfdp_offset & 0xFF00) >> 8; sfdp_cmd[3] = (sfdp_offset & 0xFF); - sfdp_cmd[4] = 0; /* Required dummy cycle. */ + sfdp_cmd[4] = 0; /* Required extra cycle. */ return spi_transaction(&spi_devices[spi_nor_device->spi_master], sfdp_cmd, 5, (uint8_t *)out_dw, 4); } diff --git a/common/test_util.c b/common/test_util.c index 0fc6306c70..704fa1d018 100644 --- a/common/test_util.c +++ b/common/test_util.c @@ -31,13 +31,13 @@ int __test_error_count; /* Weak reference function as an entry point for unit test */ test_mockable void run_test(int argc, char **argv) { } -/* Default dummy test init */ +/* Default mock test init */ test_mockable void test_init(void) { } -/* Default dummy before test */ +/* Default mock before test */ test_mockable void before_test(void) { } -/* Default dummy after test */ +/* Default mock after test */ test_mockable void after_test(void) { } #ifdef TEST_COVERAGE diff --git a/core/cortex-m/init.S b/core/cortex-m/init.S index 5b7afb2ed8..19b98b0afb 100644 --- a/core/cortex-m/init.S +++ b/core/cortex-m/init.S @@ -103,7 +103,7 @@ _data_end: _data_lma_start: .long __data_lma_start -/* Dummy functions to avoid linker complaints */ +/* Mock functions to avoid linker complaints */ .global __aeabi_unwind_cpp_pr0 .global __aeabi_unwind_cpp_pr1 .global __aeabi_unwind_cpp_pr2 diff --git a/core/cortex-m/irq_handler.h b/core/cortex-m/irq_handler.h index 657a494c93..ae5d95cd94 100644 --- a/core/cortex-m/irq_handler.h +++ b/core/cortex-m/irq_handler.h @@ -25,7 +25,7 @@ #define DECLARE_IRQ_(irq, routine, priority) \ void IRQ_HANDLER(irq)(void) __attribute__((naked)); \ typedef struct { \ - int dummy[irq >= CONFIG_IRQ_COUNT ? -1 : 1]; \ + int fake[irq >= CONFIG_IRQ_COUNT ? -1 : 1]; \ } irq_num_check_##irq; \ void __keep routine(void); \ void IRQ_HANDLER(irq)(void) \ diff --git a/core/cortex-m/switch.S b/core/cortex-m/switch.S index ae76b64c37..f56c5e4c74 100644 --- a/core/cortex-m/switch.S +++ b/core/cortex-m/switch.S @@ -80,7 +80,7 @@ __switchto: .global __task_start .thumb_func __task_start: - ldr r2,=scratchpad @ area used as dummy thread stack for the first switch + ldr r2,=scratchpad @ area used as thread stack for the first switch mov r3, #2 @ use : priv. mode / thread stack / no floating point @ setting FP to unused here means first context switch @ will not store FP regs diff --git a/core/cortex-m0/init.S b/core/cortex-m0/init.S index c76f5a3ba3..5047d18380 100644 --- a/core/cortex-m0/init.S +++ b/core/cortex-m0/init.S @@ -111,7 +111,7 @@ _data_end: _data_lma_start: .long __data_lma_start -/* Dummy functions to avoid linker complaints */ +/* Mock functions to avoid linker complaints */ .global __aeabi_unwind_cpp_pr0 .global __aeabi_unwind_cpp_pr1 .global __aeabi_unwind_cpp_pr2 diff --git a/core/cortex-m0/switch.S b/core/cortex-m0/switch.S index ed1148e21b..a27d929816 100644 --- a/core/cortex-m0/switch.S +++ b/core/cortex-m0/switch.S @@ -64,7 +64,7 @@ __switchto: .global __task_start .thumb_func __task_start: - ldr r2,=scratchpad @ area used as dummy thread stack for the first switch + ldr r2,=scratchpad @ area used as thread stack for the first switch movs r3, #2 @ use : priv. mode / thread stack / no floating point adds r2, #17*4 @ put the pointer at the top of the stack movs r1, #0 @ __Schedule parameter : re-schedule nothing diff --git a/core/nds32/switch.S b/core/nds32/switch.S index 95a94e63e5..11fc0d76cd 100644 --- a/core/nds32/switch.S +++ b/core/nds32/switch.S @@ -80,7 +80,7 @@ __switch_task: */ .global __task_start __task_start: - /* area used as dummy thread stack for the first switch */ + /* area used as thread stack for the first switch */ la $r3, scratchpad movi55 $r4, 1 @@ -88,7 +88,7 @@ __task_start: movi55 $r1, 0 /* syscall 2nd parameter : re-schedule nothing */ movi55 $r0, 0 /* syscall 1st parameter : de-schedule nothing */ - /* put the dummy stack pointer at the top of the stack in scratchpad */ + /* put the stack pointer at the top of the stack in scratchpad */ addi $sp, $r3, 4 * 18 /* we are ready to re-schedule */ swi.gp $r4, [ + need_resched] diff --git a/core/riscv-rv32i/switch.S b/core/riscv-rv32i/switch.S index b31e75076a..d6c00b8591 100644 --- a/core/riscv-rv32i/switch.S +++ b/core/riscv-rv32i/switch.S @@ -148,13 +148,13 @@ __switch_task: .global __task_start __task_start: csrci mstatus, 0x8 - /* area used as dummy thread stack for the first switch */ + /* area used as thread stack for the first switch */ la a3, scratchpad li a4, 1 li a2, 0 /* system call 3rd parameter : not an IRQ emulation */ li a1, 0 /* system call 2nd parameter : re-schedule nothing */ li a0, 0 /* system call 1st parameter : de-schedule nothing */ - /* put the dummy stack pointer at the top of the stack in scratchpad */ + /* put the stack pointer at the top of the stack in scratchpad */ addi sp, a3, 4 * TASK_SCRATCHPAD_SIZE /* we are ready to re-schedule */ la t0, need_resched diff --git a/docs/ap-ec-comm.md b/docs/ap-ec-comm.md index 8b6b5abe41..a65c419171 100644 --- a/docs/ap-ec-comm.md +++ b/docs/ap-ec-comm.md @@ -128,7 +128,7 @@ embedded controllers either aren't fast enough or don't have any support for hardware flow-control. It works like this: When the AP sends a byte to the EC, if the EC doesn't have a -response queued up in advance, a default "dummy" byte is returned. The EC +response queued up in advance, a default byte is returned. The EC preconfigures that default response byte to indicate its status (ready, busy, waiting for more input, etc.). Once the AP has sent a complete command message, it continues clocking bytes to the EC (which the EC ignores) and just looks at diff --git a/docs/configuration/gpio.md b/docs/configuration/gpio.md index 86fd21db6a..4e13a7cb59 100644 --- a/docs/configuration/gpio.md +++ b/docs/configuration/gpio.md @@ -10,7 +10,7 @@ the pins on the EC chipset through the following macros. longer required. - `ALTERNATE(...)` - Configures a pin for an alternate function (e.g I2C, ADC, SPI, etc) -- `UNIMPLEMENTED(<name>, ...)` - Creates a dummy GPIO entry +- `UNIMPLEMENTED(<name>, ...)` - Creates a fake GPIO entry The `GPIO()`, `GPIO_INT()`, and `UNIMPLEMENTED()` macros create a C enumeration of the form `GPIO_<name>` that can be used in the code. As noted in [GPIO diff --git a/driver/charger/rt946x.c b/driver/charger/rt946x.c index e139161a31..d78089439c 100644 --- a/driver/charger/rt946x.c +++ b/driver/charger/rt946x.c @@ -567,7 +567,7 @@ static int rt946x_set_iprec(int chgnum, unsigned int iprec) static int rt946x_init_irq(int chgnum) { int rv = 0; - int dummy; + int unused; int i; /* Mask all interrupts */ @@ -578,7 +578,7 @@ static int rt946x_init_irq(int chgnum) /* Clear all interrupt flags */ for (i = 0; i < RT946X_IRQ_COUNT; i++) { - rv = rt946x_read8(chgnum, RT946X_REG_CHGSTATC + i, &dummy); + rv = rt946x_read8(chgnum, RT946X_REG_CHGSTATC + i, &unused); if (rv) return rv; } diff --git a/driver/tcpm/ps8xxx.c b/driver/tcpm/ps8xxx.c index 042f928aba..9c65048c39 100644 --- a/driver/tcpm/ps8xxx.c +++ b/driver/tcpm/ps8xxx.c @@ -392,7 +392,7 @@ static int ps8xxx_tcpm_init(int port) * as though a port partner is detected), which ends up confusing * our TCPM. The workaround for this seems to be a short sleep and * then re-reading the CC state. In other words, the issue shows up - * as a short glitch or transient, which a dummy read and then a short + * as a short glitch or transient, which an extra read and then a short * delay will allow the transient to disappear. */ static int ps8751_get_gcc(int port, enum tcpc_cc_voltage_status *cc1, diff --git a/driver/touchpad_st.c b/driver/touchpad_st.c index a49ab2d7e2..c5211dcead 100644 --- a/driver/touchpad_st.c +++ b/driver/touchpad_st.c @@ -102,8 +102,8 @@ static uint32_t irq_ts; static struct st_tp_system_info_t system_info; static struct { -#if ST_TP_DUMMY_BYTE == 1 - uint8_t dummy; +#if ST_TP_EXTRA_BYTE == 1 + uint8_t extra_byte; #endif union { uint8_t bytes[512]; @@ -341,7 +341,7 @@ static int st_tp_read_report(void) static int st_tp_read_host_buffer_header(void) { const uint8_t tx_buf[] = { ST_TP_CMD_READ_SPI_HOST_BUFFER, 0x00, 0x00 }; - int rx_len = ST_TP_DUMMY_BYTE + sizeof(rx_buf.buffer_header); + int rx_len = ST_TP_EXTRA_BYTE + sizeof(rx_buf.buffer_header); return spi_transaction(SPI, tx_buf, sizeof(tx_buf), (uint8_t *)&rx_buf, rx_len); @@ -479,7 +479,7 @@ static int st_tp_load_host_data(uint8_t mem_id) int retry, ret; uint16_t count; struct st_tp_host_data_header_t *header = &rx_buf.data_header; - int rx_len = sizeof(*header) + ST_TP_DUMMY_BYTE; + int rx_len = sizeof(*header) + ST_TP_EXTRA_BYTE; st_tp_read_host_data_memory(0x0000, &rx_buf, rx_len); if (header->host_data_mem_id == mem_id) @@ -515,7 +515,7 @@ static int st_tp_load_host_data(uint8_t mem_id) static int st_tp_read_system_info(int reload) { int ret = EC_SUCCESS; - int rx_len = ST_TP_DUMMY_BYTE + ST_TP_SYSTEM_INFO_LEN; + int rx_len = ST_TP_EXTRA_BYTE + ST_TP_SYSTEM_INFO_LEN; uint8_t *ptr = rx_buf.bytes; if (reload) @@ -567,7 +567,7 @@ static void enable_deep_sleep(int enable) static void dump_error(void) { uint8_t tx_buf[] = {0xFB, 0x20, 0x01, 0xEF, 0x80}; - int rx_len = sizeof(rx_buf.dump_info) + ST_TP_DUMMY_BYTE; + int rx_len = sizeof(rx_buf.dump_info) + ST_TP_EXTRA_BYTE; int i; spi_transaction(SPI, tx_buf, sizeof(tx_buf), @@ -588,7 +588,7 @@ static void dump_error(void) */ static void dump_memory(void) { - uint32_t size = 0x10000, rx_len = 512 + ST_TP_DUMMY_BYTE; + uint32_t size = 0x10000, rx_len = 512 + ST_TP_EXTRA_BYTE; uint32_t offset, i; uint8_t cmd[] = {0xFB, 0x00, 0x10, 0x00, 0x00}; @@ -601,7 +601,7 @@ static void dump_memory(void) spi_transaction(SPI, cmd, sizeof(cmd), (uint8_t *)&rx_buf, rx_len); - for (i = 0; i < rx_len - ST_TP_DUMMY_BYTE; i += 32) { + for (i = 0; i < rx_len - ST_TP_EXTRA_BYTE; i += 32) { CPRINTF("%ph %ph %ph %ph " "%ph %ph %ph %ph\n", HEX_BUF(rx_buf.bytes + i + 4 * 0, 4), @@ -750,7 +750,7 @@ static void st_tp_handle_status_report(struct st_tp_event_t *e) static int st_tp_read_all_events(int show_error) { uint8_t cmd = ST_TP_CMD_READ_ALL_EVENTS; - int rx_len = sizeof(rx_buf.events) + ST_TP_DUMMY_BYTE; + int rx_len = sizeof(rx_buf.events) + ST_TP_EXTRA_BYTE; int i; if (spi_transaction(SPI, &cmd, 1, (uint8_t *)&rx_buf, rx_len)) @@ -921,7 +921,7 @@ static int wait_for_flash_ready(uint8_t type) while (retry--) { ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf), - (uint8_t *)&rx_buf, 1 + ST_TP_DUMMY_BYTE); + (uint8_t *)&rx_buf, 1 + ST_TP_EXTRA_BYTE); if (ret == EC_SUCCESS && !(rx_buf.bytes[0] & 0x80)) break; msleep(50); @@ -1335,7 +1335,7 @@ static void touchpad_read_idle_count(void) static uint32_t prev_count; uint32_t count; int ret; - int rx_len = 2 + ST_TP_DUMMY_BYTE; + int rx_len = 2 + ST_TP_EXTRA_BYTE; uint8_t cmd_read_counter[] = { 0xFB, 0x00, 0x10, 0xff, 0xff }; @@ -1352,7 +1352,7 @@ static void touchpad_read_idle_count(void) /* Read idle count */ spi_transaction(SPI, cmd_read_counter, sizeof(cmd_read_counter), - (uint8_t *)&rx_buf, 4 + ST_TP_DUMMY_BYTE); + (uint8_t *)&rx_buf, 4 + ST_TP_EXTRA_BYTE); count = rx_buf.dump_info[0]; @@ -1386,12 +1386,12 @@ static void touchpad_collect_error(void) enable_deep_sleep(0); spi_transaction(SPI, tx_dump_error, sizeof(tx_dump_error), (uint8_t *)&rx_buf, - sizeof(dump_info) + ST_TP_DUMMY_BYTE); + sizeof(dump_info) + ST_TP_EXTRA_BYTE); memcpy(dump_info, rx_buf.bytes, sizeof(dump_info)); spi_transaction(SPI, tx_dump_memory, sizeof(tx_dump_memory), (uint8_t *)&rx_buf, - sizeof(dump_memory) + ST_TP_DUMMY_BYTE); + sizeof(dump_memory) + ST_TP_EXTRA_BYTE); memcpy(dump_memory, rx_buf.bytes, sizeof(dump_memory)); CPRINTS("check error dump: %08x %08x", dump_info[0], dump_info[1]); @@ -1578,7 +1578,7 @@ static void print_frame(void) static int st_tp_read_frame(void) { int ret = EC_SUCCESS; - int rx_len = ST_TOUCH_FRAME_SIZE + ST_TP_DUMMY_BYTE; + int rx_len = ST_TOUCH_FRAME_SIZE + ST_TP_EXTRA_BYTE; int heat_map_addr = get_heat_map_addr(); uint8_t tx_buf[] = { ST_TP_CMD_READ_SPI_HOST_BUFFER, @@ -1590,11 +1590,11 @@ static int st_tp_read_frame(void) * Since usb_packet.frame is already ane uint8_t byte array, we can just * make it the RX buffer for SPI transaction. * - * When there is a dummy byte, since we know that flags is a one byte + * When there is a extra byte, since we know that flags is a one byte * value, and we will override it later, it's okay for SPI transaction - * to write the dummy byte to flags address. + * to write the extra byte to flags address. */ -#if ST_TP_DUMMY_BYTE == 1 +#if ST_TP_EXTRA_BYTE == 1 BUILD_ASSERT(sizeof(usb_packet[0].flags) == 1); uint8_t *rx_buf = &usb_packet[spi_buffer_index & 1].flags; #else diff --git a/driver/touchpad_st.h b/driver/touchpad_st.h index ecbddcb324..a6534f278f 100644 --- a/driver/touchpad_st.h +++ b/driver/touchpad_st.h @@ -12,7 +12,7 @@ #define ST_VENDOR_ID 0x0483 -#define ST_TP_DUMMY_BYTE 1 +#define ST_TP_EXTRA_BYTE 1 #define ST_TP_CMD_READ_ALL_EVENTS 0x87 #define ST_TP_CMD_WRITE_SCAN_MODE_SELECT 0xA0 diff --git a/extra/usb_power/stats_manager_unittest.py b/extra/usb_power/stats_manager_unittest.py index 9d0d708af0..f9e5e35c84 100644 --- a/extra/usb_power/stats_manager_unittest.py +++ b/extra/usb_power/stats_manager_unittest.py @@ -22,7 +22,7 @@ class TestStatsManager(unittest.TestCase): them in expected format. """ - def _populate_dummy_stats(self): + def _populate_mock_stats(self): """Create a populated & processed StatsManager to test data retrieval.""" self.data.AddSample('A', 99999.5) self.data.AddSample('A', 100000.5) @@ -34,7 +34,7 @@ class TestStatsManager(unittest.TestCase): self.data.SetUnit('B', 'mV') self.data.CalculateStats() - def _populate_dummy_stats_no_unit(self): + def _populate_mock_stats_no_unit(self): self.data.AddSample('B', 1000) self.data.AddSample('A', 200) self.data.SetUnit('A', 'blue') @@ -112,14 +112,14 @@ class TestStatsManager(unittest.TestCase): def test_GetRawData(self): """GetRawData returns exact same data as fed in.""" - self._populate_dummy_stats() + self._populate_mock_stats() raw_data = self.data.GetRawData() self.assertListEqual([99999.5, 100000.5], raw_data['A']) self.assertListEqual([1.5, 2.5, 3.5], raw_data['B']) def test_GetSummary(self): """GetSummary returns expected stats about the data fed in.""" - self._populate_dummy_stats() + self._populate_mock_stats() summary = self.data.GetSummary() self.assertEqual(2, summary['A']['count']) self.assertAlmostEqual(100000.5, summary['A']['max']) @@ -134,7 +134,7 @@ class TestStatsManager(unittest.TestCase): def test_SaveRawData(self): """SaveRawData stores same data as fed in.""" - self._populate_dummy_stats() + self._populate_mock_stats() dirname = 'unittest_raw_data' expected_files = set(['A_mW.txt', 'B_mV.txt']) fnames = self.data.SaveRawData(self.tempdir, dirname) @@ -156,7 +156,7 @@ class TestStatsManager(unittest.TestCase): def test_SaveRawDataNoUnit(self): """SaveRawData appends no unit suffix if the unit is not specified.""" - self._populate_dummy_stats_no_unit() + self._populate_mock_stats_no_unit() self.data.CalculateStats() outdir = 'unittest_raw_data' files = self.data.SaveRawData(self.tempdir, outdir) @@ -168,7 +168,7 @@ class TestStatsManager(unittest.TestCase): """SaveRawData uses the smid when creating output filename.""" identifier = 'ec' self.data = stats_manager.StatsManager(smid=identifier) - self._populate_dummy_stats() + self._populate_mock_stats() files = self.data.SaveRawData(self.tempdir) for fname in files: self.assertTrue(os.path.basename(fname).startswith(identifier)) @@ -202,7 +202,7 @@ class TestStatsManager(unittest.TestCase): """Title shows up in SummaryToString if title specified.""" title = 'titulo' data = stats_manager.StatsManager(title=title) - self._populate_dummy_stats() + self._populate_mock_stats() summary_str = data.SummaryToString() self.assertIn(title, summary_str) @@ -241,7 +241,7 @@ class TestStatsManager(unittest.TestCase): def test_SaveSummary(self): """SaveSummary properly dumps the summary into a file.""" - self._populate_dummy_stats() + self._populate_mock_stats() fname = 'unittest_summary.txt' expected_fname = os.path.join(self.tempdir, fname) fname = self.data.SaveSummary(self.tempdir, fname) @@ -265,13 +265,13 @@ class TestStatsManager(unittest.TestCase): """SaveSummary uses the smid when creating output filename.""" identifier = 'ec' self.data = stats_manager.StatsManager(smid=identifier) - self._populate_dummy_stats() + self._populate_mock_stats() fname = os.path.basename(self.data.SaveSummary(self.tempdir)) self.assertTrue(fname.startswith(identifier)) def test_SaveSummaryJSON(self): """SaveSummaryJSON saves the added data properly in JSON format.""" - self._populate_dummy_stats() + self._populate_mock_stats() fname = 'unittest_summary.json' expected_fname = os.path.join(self.tempdir, fname) fname = self.data.SaveSummaryJSON(self.tempdir, fname) @@ -291,13 +291,13 @@ class TestStatsManager(unittest.TestCase): """SaveSummaryJSON uses the smid when creating output filename.""" identifier = 'ec' self.data = stats_manager.StatsManager(smid=identifier) - self._populate_dummy_stats() + self._populate_mock_stats() fname = os.path.basename(self.data.SaveSummaryJSON(self.tempdir)) self.assertTrue(fname.startswith(identifier)) def test_SaveSummaryJSONNoUnit(self): """SaveSummaryJSON marks unknown units properly as N/A.""" - self._populate_dummy_stats_no_unit() + self._populate_mock_stats_no_unit() self.data.CalculateStats() fname = 'unittest_summary.json' fname = self.data.SaveSummaryJSON(self.tempdir, fname) diff --git a/include/clock.h b/include/clock.h index 4b7cbd764f..acbd3fbcf5 100644 --- a/include/clock.h +++ b/include/clock.h @@ -63,7 +63,7 @@ enum bus_type { /** * Wait for a number of peripheral bus clock cycles. * - * Dummy read on peripherals for delay. + * Read on peripherals for delay. * * @param bus Which bus clock cycle to use. * @param cycles Number of cycles to wait. diff --git a/include/config.h b/include/config.h index 06d9b961aa..104b879234 100644 --- a/include/config.h +++ b/include/config.h @@ -1102,7 +1102,7 @@ #undef CONFIG_CHIPSET_COMETLAKE_DISCRETE /* Intel Cometlake (x86), * discrete EC control */ -#undef CONFIG_CHIPSET_ECDRIVEN /* Dummy power module */ +#undef CONFIG_CHIPSET_ECDRIVEN /* Mock power module */ #undef CONFIG_CHIPSET_GEMINILAKE /* Intel Geminilake (x86) */ #undef CONFIG_CHIPSET_ICELAKE /* Intel Icelake (x86) */ #undef CONFIG_CHIPSET_JASPERLAKE /* Intel Jasperlake (x86) */ diff --git a/include/gpio.wrap b/include/gpio.wrap index 8f2d7c709d..cca72ba7b0 100644 --- a/include/gpio.wrap +++ b/include/gpio.wrap @@ -94,9 +94,9 @@ * function/name then it should specify that that GPIO is not implemented using * the UNIMPLEMENTED macro below in the board gpio.inc file. This macro creates * an entry in the gpio_signal enum and the gpio_list array that is initialized - * to use the DUMMY_GPIO_BANK and a bitmask of zero. The chip GPIO layer is - * implemented such that writes to and reads from DUMMY_GPIO_BANK with a bitmask - * of zero are harmless. + * to use the UNIMPLEMENTED_GPIO_BANK and a bitmask of zero. The chip GPIO + * layer is implemented such that writes to and reads from + * UNIMPLEMENTED_GPIO_BANK with a bitmask of zero are harmless. * * This allows common code that expects these GPIOs to exist to compile and have * some reduced functionality. diff --git a/include/gpio_list.h b/include/gpio_list.h index 08d1883cf4..3c71c3b0e2 100644 --- a/include/gpio_list.h +++ b/include/gpio_list.h @@ -16,7 +16,7 @@ #define GPIO_INT(name, pin, flags, signal) {#name, GPIO_##pin, flags}, #endif -#define UNIMPLEMENTED(name) {#name, DUMMY_GPIO_BANK, 0, GPIO_DEFAULT}, +#define UNIMPLEMENTED(name) {#name, UNIMPLEMENTED_GPIO_BANK, 0, GPIO_DEFAULT}, /* GPIO signal list. */ const struct gpio_info gpio_list[] = { diff --git a/include/sfdp.h b/include/sfdp.h index 4f7ddfb21e..087708d799 100644 --- a/include/sfdp.h +++ b/include/sfdp.h @@ -32,7 +32,7 @@ /******************************************************************************/ /* SFDP Header, always located at SFDP offset 0x0. Note that the SFDP space is - * always read in 3 Byte addressing mode with a single dummy cycle, where the + * always read in 3 Byte addressing mode with a single cycle, where the * expected SFDP address space layout looks like the following: * * ------------------0x00 @@ -259,49 +259,49 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW2_N, 30, 0); * ------------------------------------------ * <31:24> : 1-1-4 Fast Read Opcode * <23:21> : 1-1-4 Fast Read Number of Mode Bits (0 if unsupported) - * <20:16> : 1-1-4 Fast Read Number of Wait States (Dummy Clocks) + * <20:16> : 1-1-4 Fast Read Number of Wait States (Wait State Clocks) * <15:8> : 1-4-4 Fast Read Opcode * <7:5> : 1-4-4 Fast Read Number of Mode Bits (0 if unsupported) - * <4:0> : 1-4-4 Fast Read Number of Wait States (Dummy CLocks) + * <4:0> : 1-4-4 Fast Read Number of Wait States (Wait State CLocks) */ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_1_4_OPCODE, 31, 24); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_1_4_MODE_BITS, 23, 21); -SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_1_4_DUMMY_CLOCKS, 20, 16); +SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, 20, 16); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, 15, 8); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, 7, 5); -SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_DUMMY_CLOCKS, 4, 0); +SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_WAIT_STATE_CLOCKS, 4, 0); #define BFPT_1_0_DWORD_3(fr114op, fr114mb, fr114dc, \ fr144op, fr144mb, fr144dc) \ (SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_OPCODE, fr114op) | \ SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_MODE_BITS, fr114mb) | \ - SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_DUMMY_CLOCKS, fr114dc) | \ + SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, fr114dc) | \ SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, fr144op) | \ SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, fr144mb) | \ - SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_DUMMY_CLOCKS, fr144dc)) + SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_WAIT_STATE_CLOCKS, fr144dc)) /* Basic Flash Parameter Table v1.0 4th DWORD * ------------------------------------------ * <31:24> : 1-2-2 Fast Read Opcode * <23:21> : 1-2-2 Fast Read Number of Mode Bits (0 if unsupported) - * <20:16> : 1-2-2 Fast Read Number of Wait States (Dummy Clocks) + * <20:16> : 1-2-2 Fast Read Number of Wait States (Wait State Clocks) * <15:8> : 1-1-2 Fast Read Opcode * <7:5> : 1-1-2 Fast Read Number of Mode Bits (0 if unsupported) - * <4:0> : 1-1-2 Fast Read Number of Wait States (Dummy CLocks) + * <4:0> : 1-1-2 Fast Read Number of Wait States (Wait State CLocks) */ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_2_2_OPCODE, 31, 24); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_2_2_MODE_BITS, 23, 21); -SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_2_2_DUMMY_CLOCKS, 20, 16); +SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, 20, 16); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, 15, 8); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, 7, 5); -SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_DUMMY_CLOCKS, 4, 0); +SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_WAIT_STATE_CLOCKS, 4, 0); #define BFPT_1_0_DWORD_4(fr122op, fr122mb, fr122dc, \ fr112op, fr112mb, fr112dc) \ (SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_OPCODE, fr122op) | \ SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_MODE_BITS, fr122mb) | \ - SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_DUMMY_CLOCKS, fr122dc) | \ + SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, fr122dc) | \ SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, fr112op) | \ SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, fr112mb) | \ - SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_DUMMY_CLOCKS, fr112dc)) + SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_WAIT_STATE_CLOCKS, fr112dc)) /* Basic Flash Parameter Table v1.0 5th DWORD * ------------------------------------------ @@ -322,32 +322,32 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW5_2_2_2_SUPPORTED, 0, 0); * ------------------------------------------ * <31:24> : 2-2-2 Fast Read Opcode * <23:21> : 2-2-2 Fast Read Number of Mode Bits (0 if unsupported) - * <20:16> : 2-2-2 Fast Read Number of Wait States (Dummy Clocks) + * <20:16> : 2-2-2 Fast Read Number of Wait States (Wait State Clocks) * <15:0> : Reserved (0xFFFF) */ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, 31, 24); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, 23, 21); -SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_DUMMY_CLOCKS, 20, 16); +SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, 20, 16); #define BFPT_1_0_DWORD_6(fr222op, fr222mb, fr222dc) \ (SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, fr222op) | \ SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, fr222mb) | \ - SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_DUMMY_CLOCKS, fr222dc) | \ + SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, fr222dc) | \ SFDP_UNUSED(15, 0)) /* Basic Flash Parameter Table v1.0 7th DWORD * ------------------------------------------ * <31:24> : 4-4-4 Fast Read Opcode * <23:21> : 4-4-4 Fast Read Number of Mode Bits (0 if unsupported) - * <20:16> : 4-4-4 Fast Read Number of Wait States (Dummy Clocks) + * <20:16> : 4-4-4 Fast Read Number of Wait States (Wait State Clocks) * <15:0> : Reserved (0xFFFF) */ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, 31, 24); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, 23, 21); -SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_DUMMY_CLOCKS, 20, 16); +SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_WAIT_STATE_CLOCKS, 20, 16); #define BFPT_1_0_DWORD_7(fr444op, fr444mb, fr444dc) \ (SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, fr444op) | \ SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, fr444mb) | \ - SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_DUMMY_CLOCKS, fr444dc) | \ + SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_WAIT_STATE_CLOCKS, fr444dc) | \ SFDP_UNUSED(15, 0)) /* Basic Flash Parameter Table v1.0 8th DWORD diff --git a/include/spi.h b/include/spi.h index ad087a6ffc..79ed7474fa 100644 --- a/include/spi.h +++ b/include/spi.h @@ -72,7 +72,7 @@ int spi_enable(int port, int enable); * Issue a SPI transaction. Assumes SPI port has already been enabled. * * Transmits <txlen> bytes from <txdata>, throwing away the corresponding - * received data, then transmits <rxlen> dummy bytes, saving the received data + * received data, then transmits <rxlen> bytes, saving the received data * in <rxdata>. * If SPI_READBACK_ALL is set in <rxlen>, the received data during transmission * is recorded in rxdata buffer and it assumes that the real <rxlen> is equal diff --git a/include/usb_charge.h b/include/usb_charge.h index d5142ac8e9..dd0f221c28 100644 --- a/include/usb_charge.h +++ b/include/usb_charge.h @@ -82,7 +82,7 @@ int usb_charge_set_mode(int usb_port_id, enum usb_charge_mode mode, #define USB_CHG_PORT_TO_TASK_ID(port) (TASK_ID_USB_CHG_P0 + (port)) #define TASK_ID_TO_USB_CHG_PORT(id) ((id) - TASK_ID_USB_CHG_P0) #else -#define USB_CHG_PORT_TO_TASK_ID(port) -1 /* dummy task ID */ +#define USB_CHG_PORT_TO_TASK_ID(port) -1 /* stub task ID */ #define TASK_ID_TO_USB_CHG_PORT(id) 0 #endif /* HAS_TASK_USB_CHG_P0 */ diff --git a/include/usb_pd.h b/include/usb_pd.h index 4012007721..2a6558429f 100644 --- a/include/usb_pd.h +++ b/include/usb_pd.h @@ -29,7 +29,7 @@ #define PD_PORT_TO_TASK_ID(port) (TASK_ID_PD_C0 + (port)) #define TASK_ID_TO_PD_PORT(id) ((id) - TASK_ID_PD_C0) #else -#define PD_PORT_TO_TASK_ID(port) -1 /* dummy task ID */ +#define PD_PORT_TO_TASK_ID(port) -1 /* stub task ID */ #define TASK_ID_TO_PD_PORT(id) 0 #endif /* HAS_TASK_PD_C0 */ #endif /* CONFIG_USB_PD_PORT_MAX_COUNT */ diff --git a/power/ec_driven.c b/power/ec_driven.c index 7c4a021561..282941b941 100644 --- a/power/ec_driven.c +++ b/power/ec_driven.c @@ -4,7 +4,7 @@ */ /* - * Dummy power module for Sensor HUB. + * Mock power module for Sensor HUB. * * This implements the following features: * when AP_IN_SUSPEND is low, in S0, otherwise S3. diff --git a/test/charge_ramp.c b/test/charge_ramp.c index d239081c1c..acffdadbf8 100644 --- a/test/charge_ramp.c +++ b/test/charge_ramp.c @@ -59,7 +59,7 @@ int chg_ramp_max(int port, int supplier, int sup_curr) return 3000; } -/* Dummy bc12_ports[] array to make linker happy */ +/* Mock bc12_ports[] array to make linker happy */ struct bc12_config bc12_ports[0]; int charge_is_consuming_full_input_current(void) diff --git a/test/queue.c b/test/queue.c index e9f791eb3d..4e12fb147b 100644 --- a/test/queue.c +++ b/test/queue.c @@ -18,11 +18,11 @@ static struct queue const test_queue2 = QUEUE_NULL(2, int16_t); static int test_queue8_empty(void) { - char dummy = 1; + char tmp = 1; TEST_ASSERT(queue_is_empty(&test_queue8)); - TEST_ASSERT(!queue_remove_units(&test_queue8, &dummy, 1)); - TEST_ASSERT(queue_add_units(&test_queue8, &dummy, 1) == 1); + TEST_ASSERT(!queue_remove_units(&test_queue8, &tmp, 1)); + TEST_ASSERT(queue_add_units(&test_queue8, &tmp, 1) == 1); TEST_ASSERT(!queue_is_empty(&test_queue8)); return EC_SUCCESS; @@ -30,9 +30,9 @@ static int test_queue8_empty(void) static int test_queue8_init(void) { - char dummy = 1; + char tmp = 1; - TEST_ASSERT(queue_add_units(&test_queue8, &dummy, 1) == 1); + TEST_ASSERT(queue_add_units(&test_queue8, &tmp, 1) == 1); queue_init(&test_queue8); TEST_ASSERT(queue_is_empty(&test_queue8)); diff --git a/test/stress.c b/test/stress.c index 96689d840c..d975e87a84 100644 --- a/test/stress.c +++ b/test/stress.c @@ -79,25 +79,25 @@ static int stress(const char *name, static int test_i2c(void) { int res = EC_ERROR_UNKNOWN; - int dummy_data; + int mock_data; struct i2c_test_param_t *param; param = i2c_test_params + (prng_no_seed() % (sizeof(i2c_test_params) / sizeof(struct i2c_test_param_t))); if (param->width == 8 && param->data == -1) res = i2c_read8(param->port, param->addr, - param->offset, &dummy_data); + param->offset, &mock_data); else if (param->width == 8 && param->data >= 0) res = i2c_write8(param->port, param->addr, param->offset, param->data); else if (param->width == 16 && param->data == -1) res = i2c_read16(param->port, param->addr, - param->offset, &dummy_data); + param->offset, &mock_data); else if (param->width == 16 && param->data >= 0) res = i2c_write16(param->port, param->addr, param->offset, param->data); else if (param->width == 32 && param->data == -1) res = i2c_read32(param->port, param->addr, - param->offset, &dummy_data); + param->offset, &mock_data); else if (param->width == 32 && param->data >= 0) res = i2c_write32(param->port, param->addr, param->offset, param->data); diff --git a/test/thermal.c b/test/thermal.c index 2ffd4fe6ad..1161ecbf1b 100644 --- a/test/thermal.c +++ b/test/thermal.c @@ -38,7 +38,7 @@ static int cpu_shutdown; static int fan_pct; static int no_temps_read; -int dummy_temp_get_val(int idx, int *temp_ptr) +int mock_temp_get_val(int idx, int *temp_ptr) { if (mock_temp[idx] >= 0) { *temp_ptr = mock_temp[idx]; diff --git a/util/ec3po/console_unittest.py b/util/ec3po/console_unittest.py index 3c194d8419..b648f6d0c8 100755 --- a/util/ec3po/console_unittest.py +++ b/util/ec3po/console_unittest.py @@ -236,12 +236,12 @@ class TestConsoleEditingMethods(unittest.TestCase): # create a loopback. self.tempfile = tempfile.TemporaryFile() - # Create some dummy pipes. These won't be used since we'll mock out sends + # Create some mock pipes. These won't be used since we'll mock out sends # to the interpreter. - dummy_pipe_end_0, dummy_pipe_end_1 = threadproc_shim.Pipe() + mock_pipe_end_0, mock_pipe_end_1 = threadproc_shim.Pipe() self.console = console.Console(self.tempfile.fileno(), self.tempfile, tempfile.TemporaryFile(), - dummy_pipe_end_0, dummy_pipe_end_1, "EC") + mock_pipe_end_0, mock_pipe_end_1, "EC") # Console editing methods are only valid for enhanced EC images, therefore # we have to assume that the "EC" we're talking to is enhanced. By default, @@ -1142,10 +1142,10 @@ class TestConsoleCompatibility(unittest.TestCase): self.tempfile = tempfile.TemporaryFile() # Mock out the pipes. - dummy_pipe_end_0, dummy_pipe_end_1 = mock.MagicMock(), mock.MagicMock() + mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock() self.console = console.Console(self.tempfile.fileno(), self.tempfile, tempfile.TemporaryFile(), - dummy_pipe_end_0, dummy_pipe_end_1, "EC") + mock_pipe_end_0, mock_pipe_end_1, "EC") @mock.patch('console.Console.CheckForEnhancedECImage') def test_ActAsPassThruInNonEnhancedMode(self, mock_check): @@ -1412,10 +1412,10 @@ class TestOOBMConsoleCommands(unittest.TestCase): self.tempfile = tempfile.TemporaryFile() # Mock out the pipes. - dummy_pipe_end_0, dummy_pipe_end_1 = mock.MagicMock(), mock.MagicMock() + mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock() self.console = console.Console(self.tempfile.fileno(), self.tempfile, tempfile.TemporaryFile(), - dummy_pipe_end_0, dummy_pipe_end_1, "EC") + mock_pipe_end_0, mock_pipe_end_1, "EC") self.console.oobm_queue = mock.MagicMock() @mock.patch('console.Console.CheckForEnhancedECImage') diff --git a/util/stm32mon.c b/util/stm32mon.c index 7a10ceef10..6b3b0040be 100644 --- a/util/stm32mon.c +++ b/util/stm32mon.c @@ -694,7 +694,7 @@ int send_command(int fd, uint8_t cmd, payload_t *loads, int cnt, /* Read the answer payload */ if (resp) { - if (mode == MODE_SPI) /* ignore dummy byte */ + if (mode == MODE_SPI) /* ignore extra byte */ if (read_wrapper(fd, resp, 1) < 0) return STM32_EIO; while ((resp_size > 0) && diff --git a/util/uut/opr.c b/util/uut/opr.c index 81a711cf75..bc60898ce4 100644 --- a/util/uut/opr.c +++ b/util/uut/opr.c @@ -35,7 +35,6 @@ int port_handle = INVALID_HANDLE_VALUE; #define STS_MSG_MIN_SIZE 8 #define STS_MSG_APP_END 0x09 -#define DUMMY_SIZE 2 #define MAX_SYNC_TRIALS 3 |