zephyr: add bridge between zephyr gpio and cros ioex drivers

Add zephyr gpio driver that translates zephyr calls to cros ioex ones.
This allows to use cros ioex drivers on zephyr.

BRANCH=main
BUG=b:202701452
TEST=add ioex with cros driver to board dts
     check ec console for errors after sending ioexget command

Change-Id: Ib9c1d45e7f95649aadfbc9af37e805dfd6afd364
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262098
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>

9 files changed, 574 insertions, 2 deletions

diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt
index fc5a1f40fb..606500b05e 100644
--- a/zephyr/CMakeLists.txt
+++ b/zephyr/CMakeLists.txt
@@ -223,6 +223,18 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY
                                                 "${PLATFORM_EC}/common/virtual_battery.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CONSOLE_CMD_IOEX
                                                 "${PLATFORM_EC}/common/ioexpander_commands.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX_CCGXXF
+                                                "${PLATFORM_EC}/driver/ioexpander/ccgxxf.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX_IT8801
+                                                "${PLATFORM_EC}/driver/ioexpander/it8801.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX_NCT38XX
+                                                "${PLATFORM_EC}/driver/ioexpander/ioexpander_nct38xx.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX_PCA9675
+                                                "${PLATFORM_EC}/driver/ioexpander/pca9675.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX_PCAL6408
+                                                "${PLATFORM_EC}/driver/ioexpander/pcal6408.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX_TCA64XXA
+                                                "${PLATFORM_EC}/driver/ioexpander/tca64xxa.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD
                                                 "${PLATFORM_EC}/common/keyboard_scan.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042
diff --git a/zephyr/Kconfig.ioex b/zephyr/Kconfig.ioex
index 4e4cdff60d..08cedb8d2a 100644
--- a/zephyr/Kconfig.ioex
+++ b/zephyr/Kconfig.ioex
@@ -28,4 +28,45 @@ config PLATFORM_EC_CONSOLE_CMD_IOEX
 	  It will enable ioexget and ioexset commands in EC console
 	  that allow to get and change values of IO expanders pins.
 
+config PLATFORM_EC_IOEX_CROS_DRV
+	bool
+	help
+	  Enable support for CrOS EC IO expander drivers
+
+config PLATFORM_EC_IOEX_CCGXXF
+	bool "Cypress CCGXXF"
+	select PLATFORM_EC_IOEX_CROS_DRV
+	help
+	  Enables driver for Cypress CCGXXF IO expander (built inside PD chip)
+
+config PLATFORM_EC_IOEX_IT8801
+	bool "IT8801"
+	select PLATFORM_EC_IOEX_CROS_DRV
+	help
+	  Enables support for IT8801 IO expander with keyboard matrix controller
+
+config PLATFORM_EC_IOEX_NCT38XX
+	bool "Nuvoton NCT38xx"
+	select PLATFORM_EC_IOEX_CROS_DRV
+	help
+	  Enables support for IO expander built inside Nuvoton NCT38xx TCPC
+
+config PLATFORM_EC_IOEX_PCA9675
+	bool "NXP PCA9675PW"
+	select PLATFORM_EC_IOEX_CROS_DRV
+	help
+	  Enables support for NXP PCA9675PW IO expander
+
+config PLATFORM_EC_IOEX_PCAL6408
+	bool "NXP PCA(L)6408"
+	select PLATFORM_EC_IOEX_CROS_DRV
+	help
+	  Enables support for NXP PCA(L)6408 IO expander
+
+config PLATFORM_EC_IOEX_TCA64XXA
+	bool "TI TCA64xA"
+	select PLATFORM_EC_IOEX_CROS_DRV
+	help
+	  Enables support for Texas Instruments TCA64xxA IO expanders family
+
 endif
diff --git a/zephyr/dts/bindings/gpio/cros,ioex-chip.yaml b/zephyr/dts/bindings/gpio/cros,ioex-chip.yaml
new file mode 100644
index 0000000000..8ab297b035
--- /dev/null
+++ b/zephyr/dts/bindings/gpio/cros,ioex-chip.yaml
@@ -0,0 +1,50 @@
+description: IEOX chip definition
+
+compatible: "cros,ioex-chip"
+
+include: [base.yaml]
+
+properties:
+    i2c-port:
+      type: phandle
+      description:
+        Handle to the i2c named-port containing the IO expander chip
+
+    i2c-addr:
+      type: int
+      required: true
+      description:
+        I2C address of chip
+
+    flags:
+      type: int
+      required: true
+      description:
+        Value which represents IOEX_FLAGS_* or other internal flags
+        for IO expander chip.
+
+    drv:
+      type: string
+      required: true
+      description:
+        CrOS EC driver used to communicate with chip
+      enum:
+        - "ccgxxf_ioexpander_drv"
+        - "it8801_ioexpander_drv"
+        - "nct38xx_ioexpander_drv"
+        - "pca9675_ioexpander_drv"
+        - "pcal6408_ioexpander_drv"
+        - "tca64xxa_ioexpander_drv"
+
+    int-gpios:
+      type: phandle-array
+      required: false
+      description:
+        GPIO connected to the interrupt output signal of IO expander chip
+
+    "#address-cells":
+      required: true
+      const: 1
+    "#size-cells":
+      required: true
+      const: 0
\ No newline at end of file
diff --git a/zephyr/dts/bindings/gpio/cros,ioex-port.yaml b/zephyr/dts/bindings/gpio/cros,ioex-port.yaml
new file mode 100644
index 0000000000..bde3fde1ac
--- /dev/null
+++ b/zephyr/dts/bindings/gpio/cros,ioex-port.yaml
@@ -0,0 +1,26 @@
+description: IEOX port definition
+
+compatible: "cros,ioex-port"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+      description:
+        Number of port within IO expander
+
+    "#gpio-cells":
+      required: true
+      const: 2
+      description:
+        Number of parameters describing the pin
+
+    ngpios:
+      required: true
+      description:
+        Number of pins per port
+
+gpio-cells:
+  - pin
+  - flags
\ No newline at end of file
diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h
index 305173eaeb..0268734921 100644
--- a/zephyr/shim/include/config_chip.h
+++ b/zephyr/shim/include/config_chip.h
@@ -1942,4 +1942,8 @@
 #define CONFIG_AMD_STT
 #endif
 
+#ifdef CONFIG_PLATFORM_EC_IOEX_CROS_DRV
+#define CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
+#endif
+
 #endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/zephyr/shim/include/zephyr_gpio_signal.h b/zephyr/shim/include/zephyr_gpio_signal.h
index 5219982f57..e3a3752723 100644
--- a/zephyr/shim/include/zephyr_gpio_signal.h
+++ b/zephyr/shim/include/zephyr_gpio_signal.h
@@ -64,3 +64,14 @@ BUILD_ASSERT(IOEX_SIGNAL_END < IOEX_LIMIT);
 #undef IOEX_SIGNAL
 
 #define IOEX_COUNT (IOEX_SIGNAL_END - IOEX_SIGNAL_START)
+
+#define IOEXPANDER_ID_EXPAND(id) ioex_chip_##id
+#define IOEXPANDER_ID(id) IOEXPANDER_ID_EXPAND(id)
+#define IOEXPANDER_ID_FROM_INST_WITH_COMMA(id) IOEXPANDER_ID(id),
+enum ioexpander_id {
+	DT_FOREACH_STATUS_OKAY(cros_ioex_chip,
+		IOEXPANDER_ID_FROM_INST_WITH_COMMA)
+	CONFIG_IO_EXPANDER_PORT_COUNT
+};
+
+#undef IOEXPANDER_ID_FROM_INST_WITH_COMMA
diff --git a/zephyr/shim/src/CMakeLists.txt b/zephyr/shim/src/CMakeLists.txt
index 53892a3d7d..0c795f6b9b 100644
--- a/zephyr/shim/src/CMakeLists.txt
+++ b/zephyr/shim/src/CMakeLists.txt
@@ -29,6 +29,8 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD     host_command.c)
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE
                                                             console_buffer.c)
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX        ioex.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_IOEX_CROS_DRV
+                                                            ioex_drv.c)
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD    keyboard_raw.c)
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD    keyscan.c)
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MKBP_EVENT  mkbp_event.c)
diff --git a/zephyr/shim/src/ioex.c b/zephyr/shim/src/ioex.c
index 44368e5342..e01f959b65 100644
--- a/zephyr/shim/src/ioex.c
+++ b/zephyr/shim/src/ioex.c
@@ -28,8 +28,19 @@ struct ioex_gpio_config {
 	gpio_pin_t pin;
 	/* From DTS, excludes interrupts flags */
 	gpio_flags_t init_flags;
+	/*
+	 * Index of CrOS IO expander chip
+	 * If IO expander uses CrOS EC driver, this value will be one
+	 * of the possible from enum ioexpander_id
+	 * otherwise, if using the Zephyr GPIO driver, this will be -1
+	 */
+	int cros_drv_index;
+	/* Port of IO expander. Valid only if ioex field is not -1 */
+	int port;
 };
 
+#define IOEX_IS_CROS_DRV(config) (config->cros_drv_index >= 0)
+
 struct ioex_int_config {
 	const enum ioex_signal signal;
 	const gpio_flags_t flags;
@@ -69,12 +80,20 @@ struct ioex_int_config ioex_int_configs[] = {
 };
 #undef IOEX_INT
 
+#define CHIP_FROM_GPIO(id) DT_PARENT(DT_GPIO_CTLR(id, gpios))
+
 #define IOEX_GPIO_CONFIG(id)                                                \
 	{                                                                   \
 		.name = DT_LABEL(id),                                       \
 		.dev = DEVICE_DT_GET(DT_PHANDLE(id, gpios)),                \
 		.pin = DT_GPIO_PIN(id, gpios),                              \
 		.init_flags = DT_GPIO_FLAGS(id, gpios),                     \
+		.cros_drv_index =                                           \
+			COND_CODE_1(DT_NODE_HAS_COMPAT(CHIP_FROM_GPIO(id),  \
+				cros_ioex_chip),                            \
+			(IOEXPANDER_ID(CHIP_FROM_GPIO(id)), ),              \
+			(-1,))                                              \
+		.port = DT_REG_ADDR(DT_GPIO_CTLR(id, gpios))                \
 	},
 
 #define IOEX_INIT_FLAGS(id) 0,
@@ -116,6 +135,12 @@ static const struct ioex_gpio_config *ioex_get_signal_info(
 
 	g = ioex_gpio_configs + signal - IOEX_SIGNAL_START;
 
+	if (IOEX_IS_CROS_DRV(g) &&
+	    !(ioex_config[g->cros_drv_index].flags & IOEX_FLAGS_INITIALIZED)) {
+		LOG_ERR("ioex %s disabled", g->name);
+		return NULL;
+	}
+
 	return g;
 }
 
@@ -239,6 +264,20 @@ static void ioex_isr(const struct device *port,
 
 int ioex_init(int ioex)
 {
+	const struct ioexpander_drv *drv = ioex_config[ioex].drv;
+	int rv;
+
+	if (ioex_config[ioex].flags & IOEX_FLAGS_INITIALIZED)
+		return EC_SUCCESS;
+
+	if (drv->init != NULL) {
+		rv = drv->init(ioex);
+		if (rv != EC_SUCCESS)
+			return rv;
+	}
+
+	ioex_config[ioex].flags |= IOEX_FLAGS_INITIALIZED;
+
 	return EC_SUCCESS;
 }
 
@@ -319,8 +358,14 @@ int ioex_get_ioex_flags(enum ioex_signal signal, int *val)
 	if (g == NULL)
 		return EC_ERROR_INVAL;
 
-	/* Zephyr gpio drivers are initialized by internal subsystem */
-	*val = IOEX_FLAGS_INITIALIZED;
+	if (!IOEX_IS_CROS_DRV(g)) {
+		/* Zephyr gpio drivers are initialized by internal subsystem */
+		*val = IOEX_FLAGS_INITIALIZED;
+		return EC_SUCCESS;
+	}
+
+	*val = ioex_config[g->cros_drv_index].flags;
+
 	return EC_SUCCESS;
 }
 
diff --git a/zephyr/shim/src/ioex_drv.c b/zephyr/shim/src/ioex_drv.c
new file mode 100644
index 0000000000..a6075de59a
--- /dev/null
+++ b/zephyr/shim/src/ioex_drv.c
@@ -0,0 +1,381 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT cros_ioex_port
+#define DT_DRV_COMPAT_CHIP cros_ioex_chip
+
+#include <device.h>
+#include <drivers/gpio.h>
+#include <drivers/i2c.h>
+#include <errno.h>
+#include <gpio/gpio_utils.h>
+#include <init.h>
+#include <kernel.h>
+#include <logging/log.h>
+#include <sys/byteorder.h>
+#include <sys/util.h>
+#include "common.h"
+#include "config.h"
+#include "i2c.h"
+#include "ioexpander.h"
+
+/* Include drivers if enabled */
+#ifdef CONFIG_PLATFORM_EC_IOEX_CCGXXF
+#include "driver/tcpm/ccgxxf.h"
+#endif
+#ifdef CONFIG_PLATFORM_EC_IOEX_IT8801
+#include "driver/ioexpander/it8801.h"
+#endif
+#ifdef CONFIG_PLATFORM_EC_IOEX_NCT38XX
+#include "driver/tcpm/nct38xx.h"
+#endif
+#ifdef CONFIG_PLATFORM_EC_IOEX_PCA9675
+#include "driver/ioexpander/pca9675.h"
+#endif
+#ifdef CONFIG_PLATFORM_EC_IOEX_PCAL6408
+#include "driver/ioexpander/pcal6408.h"
+#endif
+#ifdef CONFIG_PLATFORM_EC_IOEX_TCA64XXA
+#include "driver/ioexpander/tca64xxa.h"
+#endif
+
+LOG_MODULE_REGISTER(cros_ioex_port, CONFIG_GPIO_LOG_LEVEL);
+
+struct ioex_drv_data {
+	const struct device *dev;
+	int ioex;
+	int port;
+
+	sys_slist_t callbacks;
+	struct k_work worker;
+
+	const struct device *int_gpio_dev;
+	gpio_pin_t int_gpio_pin;
+	gpio_flags_t int_gpio_flags;
+	struct gpio_callback int_gpio_callback;
+	gpio_port_value_t cached_values;
+	gpio_port_value_t pin_trig_edge_rising;
+	gpio_port_value_t pin_trig_edge_falling;
+	gpio_port_value_t pin_trig_level_zero;
+	gpio_port_value_t pin_trig_level_one;
+};
+
+static int shim_ioex_pin_configure(const struct device *dev, gpio_pin_t pin,
+				   gpio_flags_t flags)
+{
+	const struct ioexpander_config_t *cfg = dev->config;
+	struct ioex_drv_data *drv_data = dev->data;
+	int res;
+
+	res = cfg->drv->set_flags_by_mask(drv_data->ioex, drv_data->port,
+					  BIT(pin),
+					  convert_from_zephyr_flags(flags));
+	if (res)
+		return -EIO;
+
+	return 0;
+}
+
+static int shim_ioex_port_get_raw(const struct device *dev,
+				  gpio_port_value_t *value)
+{
+	const struct ioexpander_config_t *cfg = dev->config;
+	struct ioex_drv_data *drv_data = dev->data;
+	int res;
+
+	res = cfg->drv->get_port(drv_data->ioex, drv_data->port, value);
+	if (res)
+		return -EIO;
+
+	return 0;
+}
+
+static int shim_ioex_port_set_masked_raw(const struct device *dev,
+					 gpio_port_pins_t mask,
+					 gpio_port_value_t value)
+{
+	const struct ioexpander_config_t *cfg = dev->config;
+	struct ioex_drv_data *drv_data = dev->data;
+	int res;
+
+	res = cfg->drv->set_level(drv_data->ioex, drv_data->port, mask, value);
+	if (res)
+		return -EIO;
+
+	return 0;
+}
+
+static int shim_ioex_port_set_bits_raw(const struct device *dev,
+				       gpio_port_pins_t pins)
+{
+	const struct ioexpander_config_t *cfg = dev->config;
+	struct ioex_drv_data *drv_data = dev->data;
+	int res;
+
+	res = cfg->drv->set_level(drv_data->ioex, drv_data->port, pins, 1);
+	if (res)
+		return -EIO;
+
+	return 0;
+}
+
+static int shim_ioex_port_clear_bits_raw(const struct device *dev,
+					 gpio_port_pins_t pins)
+{
+	const struct ioexpander_config_t *cfg = dev->config;
+	struct ioex_drv_data *drv_data = dev->data;
+	int res;
+
+	res = cfg->drv->set_level(drv_data->ioex, drv_data->port, pins, 0);
+	if (res)
+		return -EIO;
+
+	return 0;
+}
+
+static int shim_ioex_port_toggle_bits(const struct device *dev,
+				      gpio_port_pins_t pins)
+{
+	const struct ioexpander_config_t *cfg = dev->config;
+	struct ioex_drv_data *drv_data = dev->data;
+	int to_set;
+	int to_clr;
+	int res;
+	int val;
+
+	res = cfg->drv->get_port(drv_data->ioex, drv_data->port, &val);
+	if (res)
+		return -EIO;
+
+	to_set = (~val) & pins;
+	to_clr = val & pins;
+
+	res = cfg->drv->set_level(drv_data->ioex, drv_data->port, to_set, 1);
+	if (res)
+		return -EIO;
+
+	res = cfg->drv->set_level(drv_data->ioex, drv_data->port, to_clr, 0);
+	if (res)
+		return -EIO;
+
+	return 0;
+}
+
+static int shim_ioex_pin_interrupt_configure(const struct device *dev,
+					     gpio_pin_t pin,
+					     enum gpio_int_mode mode,
+					     enum gpio_int_trig trig)
+{
+	const struct ioexpander_config_t *cfg = dev->config;
+	struct ioex_drv_data *drv_data = dev->data;
+	int flags;
+	int res;
+
+	if (!drv_data->int_gpio_dev) {
+		LOG_ERR("Trying to enable interrupt on ioex %d without "
+			"defined IO expander interrupt pin",
+			drv_data->ioex);
+		return -EIO;
+	}
+
+	res = cfg->drv->get_flags_by_mask(drv_data->ioex, drv_data->port,
+					  BIT(pin), &flags);
+	if (res)
+		return -EIO;
+
+	flags |= convert_from_zephyr_flags(mode | trig);
+
+	res = cfg->drv->set_flags_by_mask(drv_data->ioex, drv_data->port,
+					  BIT(pin), flags);
+	if (res)
+		return -EIO;
+
+	if (!cfg->drv->enable_interrupt) {
+		LOG_ERR("Trying to enable interrupt on ioex %d which doesn't "
+			"support interrupts",
+			drv_data->ioex);
+		return -EIO;
+	}
+
+	res = cfg->drv->enable_interrupt(drv_data->ioex, drv_data->port,
+					 BIT(pin), (mode & GPIO_INT_ENABLE));
+	if (res)
+		return -EIO;
+
+	if (mode == GPIO_INT_MODE_DISABLED) {
+		drv_data->pin_trig_edge_rising &= ~BIT(pin);
+		drv_data->pin_trig_edge_falling &= ~BIT(pin);
+		drv_data->pin_trig_level_zero &= ~BIT(pin);
+		drv_data->pin_trig_level_one &= ~BIT(pin);
+	} else if (mode == GPIO_INT_MODE_EDGE) {
+		if (trig & GPIO_INT_LOW_0)
+			drv_data->pin_trig_edge_falling |= BIT(pin);
+		if (trig & GPIO_INT_HIGH_1)
+			drv_data->pin_trig_edge_rising |= BIT(pin);
+	} else {
+		if (trig & GPIO_INT_LOW_0)
+			drv_data->pin_trig_level_zero |= BIT(pin);
+		if (trig & GPIO_INT_HIGH_1)
+			drv_data->pin_trig_level_one |= BIT(pin);
+	}
+
+	return 0;
+}
+
+static void shim_ioex_isr(const struct device *dev,
+			  struct gpio_callback *callback, gpio_port_pins_t pins)
+{
+	struct ioex_drv_data *drv_data =
+		CONTAINER_OF(callback, struct ioex_drv_data, int_gpio_callback);
+
+	k_work_submit(&drv_data->worker);
+}
+
+static void shim_ioex_worker(struct k_work *worker)
+{
+	struct ioex_drv_data *drv_data =
+		CONTAINER_OF(worker, struct ioex_drv_data, worker);
+	const struct ioexpander_drv *drv = ioex_config[drv_data->ioex].drv;
+	int interrupted_pins_level = 0;
+	int interrupted_pins_edge = 0;
+	int interrupted_pins = 0;
+	int current_values;
+	int changed_pins;
+
+	if (drv_data->ioex < 0) {
+		LOG_ERR("Invalid int IOEX");
+		return;
+	}
+
+	if (!drv->get_port) {
+		LOG_ERR("IO expander doesn't support get_port function");
+		return;
+	}
+
+	if (drv->get_port(drv_data->ioex, drv_data->port, &current_values)) {
+		LOG_ERR("Couldn't get int ioex values");
+		return;
+	}
+
+	changed_pins = current_values ^ drv_data->cached_values;
+
+	/* Edge rising */
+	interrupted_pins_edge |= (changed_pins & current_values) &
+				 drv_data->pin_trig_edge_rising;
+	/* Edge falling */
+	interrupted_pins_edge |= (changed_pins & (~current_values)) &
+				 drv_data->pin_trig_edge_falling;
+	/* Level 1 */
+	interrupted_pins_level |=
+		(current_values & drv_data->pin_trig_level_one);
+	/* Level 0 */
+	interrupted_pins_level |=
+		((~current_values) & drv_data->pin_trig_level_zero);
+
+	interrupted_pins = (interrupted_pins_edge | interrupted_pins_level);
+	gpio_fire_callbacks(&drv_data->callbacks, drv_data->dev,
+			    interrupted_pins);
+
+	drv_data->cached_values = current_values;
+
+	/* Recalling this function will simulate interrupts triggered by
+	 * logic level instead of level change (edge).
+	 * Function will be called repeatedly until the level change to value
+	 * not triggering the interrupt.
+	 */
+	if (interrupted_pins_level)
+		k_work_submit(worker);
+}
+
+static int shim_ioex_init(const struct device *dev)
+{
+	struct ioex_drv_data *drv_data = dev->data;
+
+	drv_data->dev = dev;
+
+	/* IO expander may have specified GPIO pin that should trigger
+	 * interrupt handling routines for signals on this IO expander.
+	 * If this GPIO is specified, it should be configured as interrupt
+	 * pin and should have callback assigned to it.
+	 */
+	if (drv_data->int_gpio_dev) {
+		int res;
+
+		res = gpio_pin_configure(drv_data->int_gpio_dev,
+					 drv_data->int_gpio_pin,
+					 drv_data->int_gpio_flags | GPIO_INPUT);
+		if (res)
+			return -EIO;
+
+		gpio_init_callback(&drv_data->int_gpio_callback, shim_ioex_isr,
+				   BIT(drv_data->int_gpio_pin));
+
+		res = gpio_add_callback(drv_data->int_gpio_dev,
+					&drv_data->int_gpio_callback);
+		if (res)
+			return -EIO;
+
+		k_work_init(&drv_data->worker, shim_ioex_worker);
+	}
+
+	return 0;
+}
+
+static int shim_ioex_manage_callback(const struct device *dev,
+				     struct gpio_callback *callback,
+				     bool enable)
+{
+	struct ioex_drv_data *drv_data = dev->data;
+
+	return gpio_manage_callback(&drv_data->callbacks, callback, enable);
+}
+
+static const struct gpio_driver_api api_table = {
+	.pin_configure = shim_ioex_pin_configure,
+	.port_get_raw = shim_ioex_port_get_raw,
+	.port_set_masked_raw = shim_ioex_port_set_masked_raw,
+	.port_set_bits_raw = shim_ioex_port_set_bits_raw,
+	.port_clear_bits_raw = shim_ioex_port_clear_bits_raw,
+	.port_toggle_bits = shim_ioex_port_toggle_bits,
+	.pin_interrupt_configure = shim_ioex_pin_interrupt_configure,
+	.manage_callback = shim_ioex_manage_callback,
+};
+
+#define IOEX_INIT_CONFIG_ELEM(id)                                    \
+	{                                                            \
+		.i2c_host_port = I2C_PORT(DT_PHANDLE(id, i2c_port)), \
+		.i2c_addr_flags = DT_PROP(id, i2c_addr),             \
+		.drv = &DT_STRING_TOKEN(id, drv),                    \
+		.flags = DT_PROP(id, flags),                         \
+	},
+
+#define IOEX_INIT_DATA(idx)                                                  \
+	{                                                                    \
+		.ioex = IOEXPANDER_ID(DT_PARENT(DT_DRV_INST(idx))),          \
+		.port = DT_REG_ADDR(DT_DRV_INST(idx)),                       \
+		COND_CODE_1(                                                 \
+			DT_NODE_HAS_PROP(DT_PARENT(DT_DRV_INST(idx)),        \
+					 int_gpios),                         \
+			(.int_gpio_dev = DEVICE_DT_GET(DT_PHANDLE(           \
+				 DT_PARENT(DT_DRV_INST(idx)), int_gpios)),   \
+			 .int_gpio_pin = DT_GPIO_PIN(                        \
+				 DT_PARENT(DT_DRV_INST(idx)), int_gpios),    \
+			 .int_gpio_flags = DT_GPIO_FLAGS(                    \
+				 DT_PARENT(DT_DRV_INST(idx)), int_gpios), ), \
+			())                                                  \
+	}
+
+struct ioexpander_config_t ioex_config[] = { DT_FOREACH_STATUS_OKAY(
+	DT_DRV_COMPAT_CHIP, IOEX_INIT_CONFIG_ELEM) };
+
+#define GPIO_PORT_INIT(idx)                                                  \
+	static struct ioex_drv_data ioex_##idx##_data = IOEX_INIT_DATA(idx); \
+	DEVICE_DT_INST_DEFINE(                                               \
+		idx, shim_ioex_init, NULL, &ioex_##idx##_data,               \
+		&ioex_config[IOEXPANDER_ID(DT_PARENT(DT_DRV_INST(idx)))],    \
+		POST_KERNEL, CONFIG_PLATFORM_EC_IOEX_INIT_PRIORITY,          \
+		&api_table);
+
+DT_INST_FOREACH_STATUS_OKAY(GPIO_PORT_INIT)