nissa: Initial zephyr config for nivviks

Initial EC Zephyr config for Nissa/Nivviks.
Not all GPIOs have been defined yet.
V2 - reworked to use a single project directory.
V3 - renaming.

BUG=b:201000681
TEST=make -j buildall; cd zephyr; zmake configure -b nivviks
BRANCH=none

Cq-Depend: chromium:3312397
Change-Id: I2b3f7ee77dc8365fac10b8fb7a4eec65d827bed1
Signed-off-by: Andrew McRae <amcrae@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3310024
Reviewed-by: Keith Short <keithshort@chromium.org>

8 files changed, 408 insertions, 0 deletions

diff --git a/zephyr/projects/nissa/BUILD.py b/zephyr/projects/nissa/BUILD.py
new file mode 100644
index 0000000000..f7a4473746
--- /dev/null
+++ b/zephyr/projects/nissa/BUILD.py
@@ -0,0 +1,34 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Nivviks has NPCX993F, Nereid has ITE81302
+
+
+def register_nissa_project(
+    project_name,
+    chip="it8xxx2",
+    extra_dts_overlays=(),
+    extra_kconfig_files=(),
+):
+    register_func = register_binman_project
+    if chip.startswith("npcx9"):
+        register_func = register_npcx_project
+
+    register_func(
+        project_name=project_name,
+        zephyr_board=chip,
+        dts_overlays=[*extra_dts_overlays],
+        kconfig_files=[here / "prj.conf", *extra_kconfig_files],
+    )
+
+
+register_nissa_project(
+    project_name="nivviks",
+    chip="npcx9",
+    extra_dts_overlays=[
+        here / "gpio_nivviks.dts",
+        here / "i2c_nivviks.dts",
+    ],
+    extra_kconfig_files=[here / "prj_nivviks.conf"],
+)
diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt
new file mode 100644
index 0000000000..7acb42b1bb
--- /dev/null
+++ b/zephyr/projects/nissa/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+zephyr_include_directories(include)
+
+if(DEFINED CONFIG_BOARD_NIVVIKS)
+	project(nivviks)
+endif()
diff --git a/zephyr/projects/nissa/Kconfig b/zephyr/projects/nissa/Kconfig
new file mode 100644
index 0000000000..6f6176e0dc
--- /dev/null
+++ b/zephyr/projects/nissa/Kconfig
@@ -0,0 +1,11 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_NIVVIKS
+	bool "Google Nivviks Board"
+	help
+	  Build Google Nivviks reference board. Nivviks has Intel ADL-N SoC
+	  with NPCX993FA0BX EC.
+
+source "Kconfig.zephyr"
diff --git a/zephyr/projects/nissa/gpio_nivviks.dts b/zephyr/projects/nissa/gpio_nivviks.dts
new file mode 100644
index 0000000000..7f4af90de5
--- /dev/null
+++ b/zephyr/projects/nissa/gpio_nivviks.dts
@@ -0,0 +1,144 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-gpios {
+		compatible = "named-gpios";
+
+		lid_open: lid_open {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+			label = "LID_OPEN";
+		};
+
+		gsc_ec_pwr_btn_odl: power_btn {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+			label = "GSC_EC_PWR_BTN_ODL";
+		};
+
+		wp_l {
+			gpios = <&gpioa 1 GPIO_INPUT>;
+			enum-name = "GPIO_WP_L";
+			label = "EC_WP_ODL";
+		};
+
+		ec_entering_rw {
+			gpios = <&gpio0 3 GPIO_OUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+			label = "EC_ENTERING_RW";
+		};
+
+		packet_mode_en {
+			gpios = <&gpio7 5 GPIO_OUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+			label = "EC_GSC_PACKET_MODE";
+		};
+		ec_kso_02_inv {
+			gpios = <&gpio1 7 GPIO_OUT_LOW>;
+			enum-name = "GPIO_KBD_KSO2";
+			label = "EC_KSO_02_INV";
+		};
+		pg_ec_dsw_pwrok {
+			gpios = <&gpio6 1 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_DSW_PWROK";
+			label = "EC_SOC_DSW_PWROK";
+		};
+		sys_rst_odl {
+			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_SYS_RESET_L";
+			label = "SYS_RST_ODL";
+		};
+		pg_ec_rsmrst_odl {
+			gpios = <&gpio9 4 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_RSMRST_ODL";
+			label = "RSMRST_PWRGD_L";
+		};
+		ec_pch_rsmrst_odl {
+			gpios = <&gpioa 6 GPIO_OUT_LOW>;
+			enum-name = "GPIO_PCH_RSMRST_L";
+			label = "RSMRST_PWRGD_L";
+		};
+		pg_ec_all_sys_pwrgd {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD";
+			label = "ALL_SYS_PWRGD";
+		};
+		pch_wake_odl {
+			gpios = <&gpio8 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_PCH_WAKE_ODL";
+			label = "EC_PCH_WAKE_R_ODL";
+		};
+		slp_s0_l {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S0_L";
+			label = "SLP_S0_L";
+		};
+		slp_s3_l {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S3_L";
+			label = "SLP_S3_L";
+		};
+		vccst_pwrgd_od {
+			gpios = <&gpioa 4 GPIO_ODR_LOW>;
+			enum-name = "GPIO_VCCST_PWRGD_OD";
+			label = "EC_SOC_VCCST_PWRGD_OD";
+		};
+		ec_prochot_odl {
+			gpios = <&gpiof 1 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_CPU_PROCHOT";
+			label = "EC_PROCHOT_ODL";
+		};
+		ec_pch_pwr_btn_odl {
+			gpios = <&gpioc 1 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+			label = "EC_SOC_PWR_BTN_ODL";
+		};
+		slp_sus_l {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+			enum-name = "GPIO_SLP_SUS_L";
+			label = "SLP_SUS_L";
+		};
+		pch_pwrok {
+			gpios = <&gpio3 7 GPIO_OUT_LOW>;
+			enum-name = "GPIO_PCH_PWROK";
+			label = "EC_SOC_SYS_PWROK";
+		};
+		ec_pch_sys_pwrok {
+			gpios = <&gpio7 2 GPIO_ODR_LOW>;
+			enum-name = "GPIO_EC_PCH_SYS_PWROK";
+			label = "EC_SOC_PCH_PWROK_OD";
+		};
+		ec_edp_bl_en {
+			gpios = <&gpiod 3 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+			label = "EC_EDP_BL_EN";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-pins = <
+			&gsc_ec_pwr_btn_odl
+			&lid_open
+		>;
+	};
+};
+
+/* Power switch logic input pads */
+/* LID_OPEN_OD */
+&psl_in1 {
+	flag = <NPCX_PSL_RISING_EDGE>;
+};
+
+/* ACOK_EC_OD */
+&psl_in2 {
+	flag = <NPCX_PSL_RISING_EDGE>;
+};
+
+/* GSC_EC_PWR_BTN_ODL */
+&psl_in3 {
+	flag = <NPCX_PSL_FALLING_EDGE>;
+};
diff --git a/zephyr/projects/nissa/i2c_nivviks.dts b/zephyr/projects/nissa/i2c_nivviks.dts
new file mode 100644
index 0000000000..e7fdea2b08
--- /dev/null
+++ b/zephyr/projects/nissa/i2c_nivviks.dts
@@ -0,0 +1,85 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+		eeprom {
+			i2c-port = <&i2c0_0>;
+			enum-name = "I2C_PORT_EEPROM";
+			label = "EEPROM";
+		};
+		i2c_sensor: sensor {
+			i2c-port = <&i2c1_0>;
+			enum-name = "I2C_PORT_SENSOR";
+			label = "SENSOR";
+		};
+		tcpc0 {
+			i2c-port = <&i2c3_0>;
+			enum-name = "I2C_PORT_USB_C0_TCPC";
+			label = "TCPC0";
+		};
+		tcpc1 {
+			i2c-port = <&i2c5_1>;
+			enum-name = "I2C_PORT_USB_C1_TCPC";
+			label = "TCPC1";
+		};
+		battery {
+			i2c-port = <&i2c7_0>;
+			enum-name = "I2C_PORT_BATTERY";
+			label = "BATTERY";
+		};
+	};
+};
+
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	label = "I2C_EEPROM";
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	label = "I2C_SENSOR";
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	label = "I2C_USB_C0";
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c5_1 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	label = "I2C_SUB_USB_C1";
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	label = "I2C_BATTERY";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/projects/nissa/include/gpio_map.h b/zephyr/projects/nissa/include/gpio_map.h
new file mode 100644
index 0000000000..d344e88c9b
--- /dev/null
+++ b/zephyr/projects/nissa/include/gpio_map.h
@@ -0,0 +1,48 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_GPIO_MAP_H
+#define __ZEPHYR_GPIO_MAP_H
+
+#include <devicetree.h>
+#include <gpio_signal.h>
+
+/*
+ * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
+ *
+ * Each GPIO_INT requires three parameters:
+ *   gpio_signal - The enum gpio_signal for the interrupt gpio
+ *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
+ *   handler - The platform/ec interrupt handler.
+ *
+ * Ensure that this files includes all necessary headers to declare all
+ * referenced handler functions.
+ *
+ * For example, one could use the follow definition:
+ * #define EC_CROS_GPIO_INTERRUPTS \
+ *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
+ */
+/* Helper macros for generating CROS_EC_GPIO_INTERRUPTS */
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ
+#define POWER_SIGNAL_INT(gpio, edge) \
+	GPIO_INT(gpio, edge, power_signal_interrupt)
+#define AP_PROCHOT_INT(gpio, edge) \
+	GPIO_INT(gpio, edge, throttle_ap_prochot_input_interrupt)
+#else
+#define POWER_SIGNAL_INT(gpio, edge)
+#define AP_PROCHOT_INT(gpio, edge)
+#endif
+
+
+#define EC_CROS_GPIO_INTERRUPTS                                           \
+	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)        \
+	GPIO_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH,                 \
+		 power_button_interrupt)                                  \
+	POWER_SIGNAL_INT(GPIO_SLP_SUS_L, GPIO_INT_EDGE_BOTH)              \
+	POWER_SIGNAL_INT(GPIO_PG_EC_DSW_PWROK, GPIO_INT_EDGE_BOTH)        \
+	POWER_SIGNAL_INT(GPIO_PG_EC_RSMRST_ODL, GPIO_INT_EDGE_BOTH)       \
+	POWER_SIGNAL_INT(GPIO_PG_EC_ALL_SYS_PWRGD, GPIO_INT_EDGE_BOTH)    \
+	AP_PROCHOT_INT(GPIO_EC_PROCHOT_ODL, GPIO_INT_EDGE_BOTH)
+#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/nissa/prj.conf b/zephyr/projects/nissa/prj.conf
new file mode 100644
index 0000000000..80f1d03d96
--- /dev/null
+++ b/zephyr/projects/nissa/prj.conf
@@ -0,0 +1,3 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
diff --git a/zephyr/projects/nissa/prj_nivviks.conf b/zephyr/projects/nissa/prj_nivviks.conf
new file mode 100644
index 0000000000..186cf7ff9b
--- /dev/null
+++ b/zephyr/projects/nissa/prj_nivviks.conf
@@ -0,0 +1,70 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_BRINGUP=y
+CONFIG_SHIMMED_TASKS=y
+
+# Variant config
+CONFIG_BOARD_NIVVIKS=y
+
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_SWITCH=y
+CONFIG_LTO=y
+CONFIG_CROS_FLASH_NPCX=y
+CONFIG_CROS_SYSTEM_NPCX=y
+CONFIG_PLATFORM_EC_VBOOT_EFS2=y
+CONFIG_PLATFORM_EC_VBOOT_HASH=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y
+CONFIG_PLATFORM_EC_I2C=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=y
+
+# SoC configuration
+CONFIG_AP=y
+CONFIG_AP_X86_INTEL_ADL=y
+CONFIG_FPU=y
+CONFIG_ARM_MPU=y
+
+CONFIG_ESPI=y
+CONFIG_PLATFORM_EC_ESPI=y
+CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4=y
+
+# Host command
+CONFIG_PLATFORM_EC_HOSTCMD=y
+
+CONFIG_PLATFORM_EC_ADC=n
+
+# Miscellaneous configs
+CONFIG_PLATFORM_EC_HIBERNATE_PSL=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD=y
+CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y
+CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=n
+CONFIG_PLATFORM_EC_CMD_BUTTON=n
+CONFIG_CROS_KB_RAW_NPCX=y
+
+CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y
+
+CONFIG_SYSCON=y
+
+# TODO(b/188605676): bring these features up
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=n
+CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n
+
+# Power Sequencing
+# TODO(b/203446068): Implement ADL-N power sequence.
+#CONFIG_PLATFORM_EC_POWERSEQ=y
+#CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+#CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540=y
+#CONFIG_PLATFORM_EC_POWERSEQ_RTC_RESET=n
+#CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y
+#CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
+# Treat 2nd reset from H1 as Power-On
+CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y
+CONFIG_PLATFORM_EC_THROTTLE_AP=y