pd: allow selection of Tx timer channel

So far, we always use channel 1 of the Tx timer and the configuration
code is hard coded. We need to support other channels for new Ryu
boards. Let's make this a configurable bit.

BRANCH=samus
BUG=chrome-os-partner:32660
TEST=make buildall
TEST=Plug in Zinger to Ryu and see 20V come up.

Change-Id: Id08d4eb0d6a5721d8a03672484d0892a0714383b
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223836
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>

10 files changed, 44 insertions, 17 deletions

diff --git a/board/dingdong/usb_pd_config.h b/board/dingdong/usb_pd_config.h
index 4abb3e8d51..e68eb1f662 100644
--- a/board/dingdong/usb_pd_config.h
+++ b/board/dingdong/usb_pd_config.h
@@ -22,6 +22,7 @@
 
 /* Timer channel */
 #define TIM_RX_CCR_C0 1
+#define TIM_TX_CCR_C0 1
 
 /* RX timer capture/compare register */
 #define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
@@ -51,7 +52,8 @@ static inline void spi_enable_clock(int port)
 #define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
 #define CMP2OUTSEL 0
 
-#define TIM_CCR_IDX(p) TIM_RX_CCR_C0
+#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
+#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 #define TIM_CCR_CS  1
 #define EXTI_COMP_MASK(p) (1 << 21)
 #define IRQ_COMP STM32_IRQ_COMP
diff --git a/board/firefly/usb_pd_config.h b/board/firefly/usb_pd_config.h
index e02ea286a8..77436cb74a 100644
--- a/board/firefly/usb_pd_config.h
+++ b/board/firefly/usb_pd_config.h
@@ -22,6 +22,7 @@
 
 /* Timer channel */
 #define TIM_RX_CCR_C0 1
+#define TIM_TX_CCR_C0 1
 
 /* RX timer capture/compare register */
 #define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
@@ -50,7 +51,8 @@ static inline void spi_enable_clock(int port)
 #define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
 #define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM1_IC1
 
-#define TIM_CCR_IDX(p) TIM_RX_CCR_C0
+#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
+#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 #define TIM_CCR_CS  1
 #define EXTI_COMP_MASK(p) ((1 << 21) | (1 << 22))
 #define IRQ_COMP STM32_IRQ_COMP
diff --git a/board/fruitpie/usb_pd_config.h b/board/fruitpie/usb_pd_config.h
index 4f7639c2f5..3851e9a263 100644
--- a/board/fruitpie/usb_pd_config.h
+++ b/board/fruitpie/usb_pd_config.h
@@ -22,6 +22,7 @@
 
 /* Timer channel */
 #define TIM_RX_CCR_C0 1
+#define TIM_TX_CCR_C0 1
 
 /* RX timer capture/compare register */
 #define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
@@ -51,7 +52,8 @@ static inline void spi_enable_clock(int port)
 #define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
 #define CMP2OUTSEL 0
 
-#define TIM_CCR_IDX(p) TIM_RX_CCR_C0
+#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
+#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 #define TIM_CCR_CS  1
 #define EXTI_COMP_MASK(p) (1 << 21)
 #define IRQ_COMP STM32_IRQ_COMP
diff --git a/board/hoho/usb_pd_config.h b/board/hoho/usb_pd_config.h
index 4abb3e8d51..e68eb1f662 100644
--- a/board/hoho/usb_pd_config.h
+++ b/board/hoho/usb_pd_config.h
@@ -22,6 +22,7 @@
 
 /* Timer channel */
 #define TIM_RX_CCR_C0 1
+#define TIM_TX_CCR_C0 1
 
 /* RX timer capture/compare register */
 #define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
@@ -51,7 +52,8 @@ static inline void spi_enable_clock(int port)
 #define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
 #define CMP2OUTSEL 0
 
-#define TIM_CCR_IDX(p) TIM_RX_CCR_C0
+#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
+#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 #define TIM_CCR_CS  1
 #define EXTI_COMP_MASK(p) (1 << 21)
 #define IRQ_COMP STM32_IRQ_COMP
diff --git a/board/plankton/usb_pd_config.h b/board/plankton/usb_pd_config.h
index 67e0f26542..08f6e00452 100644
--- a/board/plankton/usb_pd_config.h
+++ b/board/plankton/usb_pd_config.h
@@ -22,6 +22,7 @@
 
 /* Timer channel */
 #define TIM_RX_CCR_C0 1
+#define TIM_TX_CCR_C0 1
 
 /* RX timer capture/compare register */
 #define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
@@ -50,7 +51,8 @@ static inline void spi_enable_clock(int port)
 #define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
 #define CMP2OUTSEL 0
 
-#define TIM_CCR_IDX(p) TIM_RX_CCR_C0
+#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
+#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 #define TIM_CCR_CS  1
 #define EXTI_COMP_MASK(p) (1 << 21)
 #define IRQ_COMP STM32_IRQ_COMP
diff --git a/board/ryu/usb_pd_config.h b/board/ryu/usb_pd_config.h
index 3d7506d882..8bea5276c2 100644
--- a/board/ryu/usb_pd_config.h
+++ b/board/ryu/usb_pd_config.h
@@ -22,6 +22,7 @@
 
 /* Timer channel */
 #define TIM_RX_CCR_C0 1
+#define TIM_TX_CCR_C0 1
 
 /* RX timer capture/compare register */
 #define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
@@ -50,7 +51,8 @@ static inline void spi_enable_clock(int port)
 #define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
 #define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM1_IC1
 
-#define TIM_CCR_IDX(p) TIM_RX_CCR_C0
+#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
+#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 #define TIM_CCR_CS  1
 #define EXTI_COMP_MASK(p) ((1 << 21) | (1 << 22))
 #define IRQ_COMP STM32_IRQ_COMP
diff --git a/board/samus_pd/usb_pd_config.h b/board/samus_pd/usb_pd_config.h
index 347af9c42d..083606c413 100644
--- a/board/samus_pd/usb_pd_config.h
+++ b/board/samus_pd/usb_pd_config.h
@@ -25,6 +25,8 @@
 /* Timer channel */
 #define TIM_RX_CCR_C0 1
 #define TIM_RX_CCR_C1 1
+#define TIM_TX_CCR_C0 1
+#define TIM_TX_CCR_C1 1
 
 /* RX timer capture/compare register */
 #define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
@@ -59,7 +61,8 @@ static inline void spi_enable_clock(int port)
 #define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
 #define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM3_IC1
 
-#define TIM_CCR_IDX(p) ((p) ? TIM_RX_CCR_C1 : TIM_RX_CCR_C0)
+#define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_C1 : TIM_TX_CCR_C0)
+#define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_C1 : TIM_RX_CCR_C0)
 #define TIM_CCR_CS  1
 #define EXTI_COMP_MASK(p) ((p) ? (1<<22) : (1 << 21))
 #define IRQ_COMP STM32_IRQ_COMP
diff --git a/board/twinkie/usb_pd_config.h b/board/twinkie/usb_pd_config.h
index 2f8ab797fe..08a1dd3a15 100644
--- a/board/twinkie/usb_pd_config.h
+++ b/board/twinkie/usb_pd_config.h
@@ -30,6 +30,7 @@
 
 /* Timer channel */
 #define TIM_RX_CCR_C0 1
+#define TIM_TX_CCR_C0 1
 
 /* RX timer capture/compare register */
 #define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
@@ -52,7 +53,8 @@ static inline void spi_enable_clock(int port)
 #define CMP2OUTSEL 0
 
 #define DMAC_TIM_RX(p) STM32_DMAC_CH2
-#define TIM_CCR_IDX(p) TIM_RX_CCR_C0
+#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
+#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_CCR_CS  1
 #define EXTI_COMP_MASK(p) ((1 << 21) | (1 << 22))
 #define IRQ_COMP STM32_IRQ_COMP
diff --git a/board/zinger/usb_pd_config.h b/board/zinger/usb_pd_config.h
index 882936a9a5..c22e68858d 100644
--- a/board/zinger/usb_pd_config.h
+++ b/board/zinger/usb_pd_config.h
@@ -24,6 +24,7 @@
 
 /* Timer channel */
 #define TIM_RX_CCR_C0 1
+#define TIM_TX_CCR_C0 1
 
 /* RX timer capture/compare register */
 #define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
@@ -49,7 +50,8 @@ static inline void spi_enable_clock(int port)
 #define DMAC_SPI_TX(p) STM32_DMAC_CH3
 
 /* RX is on TIM3 CH1 connected to TIM3 CH2 pin (PA7, not internal COMP) */
-#define TIM_CCR_IDX(p) TIM_RX_CCR_C0
+#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
+#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 /* connect TIM3 CH1 to TIM3_CH2 input */
 #define TIM_CCR_CS  2
 #define EXTI_COMP_MASK(p) (1 << 7)
diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c
index 7fa2007eda..162e613cfb 100644
--- a/chip/stm32/usb_pd_phy.c
+++ b/chip/stm32/usb_pd_phy.c
@@ -472,6 +472,8 @@ void pd_hw_release(int port)
 void pd_hw_init(int port)
 {
 	struct pd_physical *phy = &pd_phy[port];
+	uint32_t val;
+
 	/* set 40 MHz pin speed on communication pins */
 	pd_set_pins_speed(port);
 
@@ -511,10 +513,16 @@ void pd_hw_init(int port)
 	/* Auto-reload value : 600000 Khz overflow */
 	phy->tim_tx->arr = TX_CLOCK_DIV;
 	/* 50% duty cycle on the output */
-	phy->tim_tx->ccr[1] = phy->tim_tx->arr / 2;
-	/* Timer CH1 output configuration */
-	phy->tim_tx->ccmr1 = (6 << 4) | (1 << 3);
-	phy->tim_tx->ccer = 1;
+	phy->tim_tx->ccr[TIM_TX_CCR_IDX(port)] = phy->tim_tx->arr / 2;
+	/* Timer channel output configuration */
+	val = (6 << 4) | (1 << 3);
+	if ((TIM_TX_CCR_IDX(port) & 1) == 0) /* CH2 or CH4 */
+		val <<= 8;
+	if (TIM_TX_CCR_IDX(port) <= 2)
+		phy->tim_tx->ccmr1 = val;
+	else
+		phy->tim_tx->ccmr2 = val;
+	phy->tim_tx->ccer = 1 << ((TIM_TX_CCR_IDX(port) - 1) * 4);
 	phy->tim_tx->bdtr = 0x8000;
 	/* set prescaler to /1 */
 	phy->tim_tx->psc = 0;
@@ -534,19 +542,19 @@ void pd_hw_init(int port)
 	/* Timeout for message receive */
 	phy->tim_rx->ccr[2] = (2400000 / 1000) * USB_PD_RX_TMOUT_US / 1000;
 	/* Timer ICx input configuration */
-	if (TIM_CCR_IDX(port) == 1)
+	if (TIM_RX_CCR_IDX(port) == 1)
 		phy->tim_rx->ccmr1 |= TIM_CCR_CS << 0;
 	else
 		/*  Unsupported RX timer capture input */
 		ASSERT(0);
 
-	phy->tim_rx->ccer = 0xB << ((TIM_CCR_IDX(port) - 1) * 4);
+	phy->tim_rx->ccer = 0xB << ((TIM_RX_CCR_IDX(port) - 1) * 4);
 	/* configure DMA request on CCRx update */
-	phy->tim_rx->dier |= 1 << (8 + TIM_CCR_IDX(port)); /* CCxDE */;
+	phy->tim_rx->dier |= 1 << (8 + TIM_RX_CCR_IDX(port)); /* CCxDE */;
 	/* set prescaler to /26 (F=1.2Mhz, T=0.8us) */
 	phy->tim_rx->psc = (clock_get_freq() / 2400000) - 1;
 	/* Reload the pre-scaler and reset the counter (clear CCRx) */
-	phy->tim_rx->egr = 0x0001 | (1 << TIM_CCR_IDX(port));
+	phy->tim_rx->egr = 0x0001 | (1 << TIM_RX_CCR_IDX(port));
 	/* clear update event from reloading */
 	phy->tim_rx->sr = 0;