waddledoo: Initial commit

This is the initial commit for waddledoo, the NPCX796FC variant of
dedede.  This commit adds ADC channels and i2c ports and some
scaffolding such that the board will compile.  More features will be
coming in subsequent commits.

BUG=b:146172102
BRANCH=None
TEST=`make -j BOARD=waddledoo`

Change-Id: I8277f6ce843fc155bd97f7f46fd96ab98cfe0881
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1988596
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>

9 files changed, 272 insertions, 3 deletions

diff --git a/baseboard/dedede/baseboard.c b/baseboard/dedede/baseboard.c
index 6a626990ca..740236d45f 100644
--- a/baseboard/dedede/baseboard.c
+++ b/baseboard/dedede/baseboard.c
@@ -6,3 +6,13 @@
 /* Dedede family-specific configuration */
 
 #include "common.h"
+#include "gpio.h"
+
+/*
+ * Dedede does not use hibernate wake pins, but the super low power "Z-state"
+ * instead in which the EC is powered off entirely.  Power will be restored to
+ * the EC once one of the wake up events occurs.  These events are ACOK, lid
+ * open, and a power button press.
+ */
+const enum gpio_signal hibernate_wake_pins[] = {};
+const int hibernate_wake_pins_used;
diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h
index c6a8aedf46..96578350bc 100644
--- a/baseboard/dedede/baseboard.h
+++ b/baseboard/dedede/baseboard.h
@@ -37,16 +37,33 @@
 #endif
 
 /* Common EC defines */
+
+/* EC Modules */
+#define CONFIG_ADC
+#define CONFIG_CRC8
 #define CONFIG_HOSTCMD_ESPI
 #define CONFIG_HOSTCMD_EVENTS
-#define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_I2C
+#define CONFIG_I2C_MASTER
+#define CONFIG_LOW_POWER_IDLE
 #define CONFIG_VBOOT_HASH
-#define CONFIG_CRC8
+#define CONFIG_VSTORE
+#define CONFIG_VSTORE_SLOT_COUNT 1
+
+/* Buttons / Switches */
+#define CONFIG_SWITCH
+#define CONFIG_WP_ACTIVE_HIGH
+
+/* CBI */
 #define CONFIG_CROS_BOARD_INFO
 #define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_LOW_POWER_IDLE
+
+/* SoC */
 #define CONFIG_BOARD_HAS_RTC_RESET
+#define CONFIG_KEYBOARD_PROTOCOL_8042
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_X86
+
 
 #ifndef __ASSEMBLER__
 
diff --git a/baseboard/dedede/build.mk b/baseboard/dedede/build.mk
index bc1b80a1da..1b2f5a51bc 100644
--- a/baseboard/dedede/build.mk
+++ b/baseboard/dedede/build.mk
@@ -7,3 +7,4 @@
 #
 
 baseboard-y=baseboard.o
+baseboard-$(VARIANT_DEDEDE_EC_NPCX796FC)+=variant_ec_npcx796fc.o
diff --git a/baseboard/dedede/variant_ec_npcx796fc.c b/baseboard/dedede/variant_ec_npcx796fc.c
new file mode 100644
index 0000000000..a8c2b8abbc
--- /dev/null
+++ b/baseboard/dedede/variant_ec_npcx796fc.c
@@ -0,0 +1,63 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Common code for VARIANT_DEDEDE_NPCX796FC configuration */
+
+#include "adc_chip.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "registers.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1] = {
+		"TEMP_SENSOR1", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+
+	[ADC_TEMP_SENSOR_2] = {
+		"TEMP_SENSOR2", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+
+	[ADC_SUB_ANALOG] = {
+		"SUB_ANALOG", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+
+	[ADC_VSNS_PP1050_ST_S] = {
+		"PP1050_ST_S_PGOOD", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1,
+		0},
+
+	[ADC_VSNS_PP3300_A] = {
+		"PP3300_A_PGOOD", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX+1,
+		0},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* I2C Ports */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		"eeprom", I2C_PORT_EEPROM, 1000, GPIO_EC_I2C_EEPROM_SCL,
+		GPIO_EC_I2C_EEPROM_SDA
+	},
+
+	{
+		"battery", I2C_PORT_BATTERY, 100, GPIO_EC_I2C_BATTERY_SCL,
+		GPIO_EC_I2C_BATTERY_SDA
+	},
+
+	{
+		"sensor", I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
+		GPIO_EC_I2C_SENSOR_SDA
+	},
+
+	{
+		"usbc0", I2C_PORT_USB_C0, 1000, GPIO_EC_I2C_USB_C0_SCL,
+		GPIO_EC_I2C_USB_C0_SDA
+	},
+
+	{
+		"sub_usbc1", I2C_PORT_SUB_USB_C1, 1000,
+		GPIO_EC_I2C_SUB_USB_C1_SCL, GPIO_EC_I2C_SUB_USB_C1_SDA
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/waddledoo/board.c b/board/waddledoo/board.c
new file mode 100644
index 0000000000..019849bd94
--- /dev/null
+++ b/board/waddledoo/board.c
@@ -0,0 +1,17 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledoo board-specific configuration */
+
+#include "adc_chip.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "lid_switch.h"
+#include "power_button.h"
+#include "switch.h"
+
+#include "gpio_list.h"
diff --git a/board/waddledoo/board.h b/board/waddledoo/board.h
new file mode 100644
index 0000000000..84a8286a91
--- /dev/null
+++ b/board/waddledoo/board.h
@@ -0,0 +1,49 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Waddledoo board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define VARIANT_DEDEDE_EC_NPCX796FC
+#include "baseboard.h"
+
+/*
+ * Remapping of schematic GPIO names to common GPIO names expected (hardcoded)
+ * in the EC code base.
+ */
+#define GPIO_EC_INT_L       GPIO_EC_AP_MKBP_INT_L
+#define GPIO_ENTERING_RW    GPIO_EC_ENTERING_RW
+#define GPIO_PCH_PWRBTN_L   GPIO_EC_AP_PWR_BTN_ODL
+#define GPIO_PCH_WAKE_L     GPIO_EC_AP_WAKE_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_WP             GPIO_EC_WP_OD
+
+/* I2C configuration */
+#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1,     /* ADC0 */
+	ADC_TEMP_SENSOR_2,     /* ADC1 */
+	ADC_SUB_ANALOG,	       /* ADC2 */
+	ADC_VSNS_PP1050_ST_S,  /* ADC3 */
+	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_CH_COUNT
+};
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/waddledoo/build.mk b/board/waddledoo/build.mk
new file mode 100644
index 0000000000..620016f814
--- /dev/null
+++ b/board/waddledoo/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+BASEBOARD:=dedede
+
+board-y=board.o
diff --git a/board/waddledoo/ec.tasklist b/board/waddledoo/ec.tasklist
new file mode 100644
index 0000000000..d2983d770d
--- /dev/null
+++ b/board/waddledoo/ec.tasklist
@@ -0,0 +1,15 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/waddledoo/gpio.inc b/board/waddledoo/gpio.inc
new file mode 100644
index 0000000000..7b1fea7541
--- /dev/null
+++ b/board/waddledoo/gpio.inc
@@ -0,0 +1,83 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
+GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+
+/* I2C Ports */
+GPIO(EC_I2C_EEPROM_SCL,	      PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_EEPROM_SDA,	      PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,	      PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SDA,	      PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SCL,	      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_SDA,	      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SCL,   PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_SUB_USB_C1_SDA,   PIN(9, 1), GPIO_INPUT)
+
+/* Extra Sub-board I/O pins */
+GPIO(EC_SUB_IO_1,  PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_SUB_IO_2,  PIN(3, 4), GPIO_OUT_LOW)
+
+/* Misc Enables */
+GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
+GPIO(EN_VCCST,	     PIN(A, 7), GPIO_OUT_LOW)
+GPIO(EN_PP3300_PEN,  PIN(6, 3), GPIO_OUT_LOW)
+GPIO(EN_PP3300_A,    PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_U,    PIN(A, 4), GPIO_OUT_LOW)
+GPIO(EN_SLP_Z,	     PIN(8, 3), GPIO_OUT_LOW)
+GPIO(EN_KB_BL,	     PIN(6, 0), GPIO_OUT_LOW)
+GPIO(EN_BL_OD,	     PIN(D, 3), GPIO_ODR_LOW)
+GPIO(IMVP9_PE,	     PIN(E, 0), GPIO_OUT_LOW)
+
+/* Power Sequencing */
+GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
+GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
+GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
+GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
+GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_OUT_HIGH)
+GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_PULL_UP | GPIO_SEL_1P8V)
+GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
+GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(RSMRST_PWRGD_L,	     PIN(C, 6), GPIO_OUT_HIGH)
+GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_INPUT)
+
+GPIO(USB_C0_RST_ODL,	     PIN(9, 7), GPIO_OUT_HIGH) /* currently unused */
+GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
+GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
+GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
+
+/* Alternate Functions */
+/* ADC */
+ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
+ALTERNATE(PIN_MASK(4, 0x3C), 0, MODULE_ADC, 0)   /* ADC0-3 */
+
+/* PWM */
+ALTERNATE(PIN_MASK(C, 0x1C), 0, MODULE_PWM, 0)   /* PWM0-2 */
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0) /* PWM3 */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
+
+/* I2C */
+ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */