diff options
author | Dino Li <Dino.Li@ite.com.tw> | 2017-12-11 12:02:16 +0800 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2017-12-12 01:05:29 -0800 |
commit | a7c08b257fff5420a584d0d8ac5529efcc111403 (patch) | |
tree | 546556c2eab3e64550df7adbb4e24e6cde0c6eb6 | |
parent | 552ca1ec4982db07a42e6d974a9f12a50a4dbc1c (diff) | |
download | chrome-ec-a7c08b257fff5420a584d0d8ac5529efcc111403.tar.gz |
it83xx: adc: add support ADC13-16
IT8320 can support extra four ADC channels (ADC13-16).
BRANCH=none
BUG=none
TEST=Run console command 'adc' and check the results.
Change-Id: Ia9a259f54fa28d43dc0050c6e20885c0b3914f9c
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/808125
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
-rw-r--r-- | board/it83xx_evb/board.c | 8 | ||||
-rw-r--r-- | board/it83xx_evb/board.h | 4 | ||||
-rw-r--r-- | board/reef_it8320/board.c | 6 | ||||
-rw-r--r-- | chip/it83xx/adc.c | 36 | ||||
-rw-r--r-- | chip/it83xx/adc_chip.h | 19 | ||||
-rw-r--r-- | chip/it83xx/registers.h | 18 |
6 files changed, 77 insertions, 14 deletions
diff --git a/board/it83xx_evb/board.c b/board/it83xx_evb/board.c index 2a4da1e126..cd0b9ff1e4 100644 --- a/board/it83xx_evb/board.c +++ b/board/it83xx_evb/board.c @@ -244,8 +244,12 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { /* Convert to mV (3000mV/1024). */ - {"ADC_VBUSSA", 3000, 1024, 0, 0}, /*GPI0*/ - {"ADC_VBUSSB", 3000, 1024, 0, 1}, /*GPI1*/ + {"ADC_VBUSSA", 3000, 1024, 0, CHIP_ADC_CH0}, /* GPI0, ADC0 */ + {"ADC_VBUSSB", 3000, 1024, 0, CHIP_ADC_CH1}, /* GPI1, ADC1 */ + {"ADC_EVB_CH_13", 3000, 1024, 0, CHIP_ADC_CH13}, /* GPL0, ADC13 */ + {"ADC_EVB_CH_14", 3000, 1024, 0, CHIP_ADC_CH14}, /* GPL1, ADC14 */ + {"ADC_EVB_CH_15", 3000, 1024, 0, CHIP_ADC_CH15}, /* GPL2, ADC15 */ + {"ADC_EVB_CH_16", 3000, 1024, 0, CHIP_ADC_CH16}, /* GPL3, ADC16 */ }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); diff --git a/board/it83xx_evb/board.h b/board/it83xx_evb/board.h index 3c7f73ae3f..ec809aa350 100644 --- a/board/it83xx_evb/board.h +++ b/board/it83xx_evb/board.h @@ -77,6 +77,10 @@ enum pwm_channel { enum adc_channel { ADC_VBUSSA, ADC_VBUSSB, + ADC_EVB_CH_13, + ADC_EVB_CH_14, + ADC_EVB_CH_15, + ADC_EVB_CH_16, /* Number of ADC channels */ ADC_CH_COUNT }; diff --git a/board/reef_it8320/board.c b/board/reef_it8320/board.c index 3cb1d49afc..ba6ad995e3 100644 --- a/board/reef_it8320/board.c +++ b/board/reef_it8320/board.c @@ -80,9 +80,9 @@ BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); /* ADC channels */ const struct adc_t adc_channels[] = { /* Convert to mV (3000mV/1024). */ - {"CHARGER", 3000, 1024, 0, 1}, /* GPI1 */ - {"AMBIENT", 3000, 1024, 0, 2}, /* GPI2 */ - {"BRD_ID", 3000, 1024, 0, 3}, /* GPI3 */ + {"CHARGER", 3000, 1024, 0, CHIP_ADC_CH1}, /* GPI1 */ + {"AMBIENT", 3000, 1024, 0, CHIP_ADC_CH2}, /* GPI2 */ + {"BRD_ID", 3000, 1024, 0, CHIP_ADC_CH3}, /* GPI3 */ }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c index f91944b1a7..6b8361dbdb 100644 --- a/chip/it83xx/adc.c +++ b/chip/it83xx/adc.c @@ -40,11 +40,20 @@ const struct adc_ctrl_t adc_ctrl_regs[] = { &IT83XX_GPIO_GPCRI6}, {&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL, &IT83XX_GPIO_GPCRI7}, + {&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL, + &IT83XX_GPIO_GPCRL0}, + {&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL, + &IT83XX_GPIO_GPCRL1}, + {&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL, + &IT83XX_GPIO_GPCRL2}, + {&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL, + &IT83XX_GPIO_GPCRL3}, }; +BUILD_ASSERT(ARRAY_SIZE(adc_ctrl_regs) == CHIP_ADC_COUNT); static void adc_enable_channel(int ch) { - if (ch < 4) + if (ch < CHIP_ADC_CH4) /* * for channel 0, 1, 2, and 3 * bit4 ~ bit0 : indicates voltage channel[x] @@ -55,8 +64,8 @@ static void adc_enable_channel(int ch) *adc_ctrl_regs[ch].adc_ctrl = 0xa0 + ch; else /* - * for channel 4, 5, 6, and 7 - * bit4 : voltage channel enable (ch 4~7 only) + * for channel 4 ~ 7 and 13 ~ 16. + * bit4 : voltage channel enable (ch 4~7 and 13 ~ 16) * bit5 : data valid interrupt of adc. * bit7 : W/C data valid flag */ @@ -71,7 +80,7 @@ static void adc_enable_channel(int ch) static void adc_disable_channel(int ch) { - if (ch < 4) + if (ch < CHIP_ADC_CH4) /* * for channel 0, 1, 2, and 3 * bit4 ~ bit0 : indicates voltage channel[x] @@ -81,8 +90,8 @@ static void adc_disable_channel(int ch) *adc_ctrl_regs[ch].adc_ctrl = 0x9F; else /* - * for channel 4, 5, 6, and 7 - * bit4 : voltage channel disable (ch 4~7 only) + * for channel 4 ~ 7 and 13 ~ 16. + * bit4 : voltage channel disable (ch 4~7 and 13 ~ 16) * bit7 : W/C data valid flag */ *adc_ctrl_regs[ch].adc_ctrl = 0x80; @@ -93,6 +102,13 @@ static void adc_disable_channel(int ch) task_disable_irq(IT83XX_IRQ_ADC); } +static int adc_data_valid(enum chip_adc_channel adc_ch) +{ + return (adc_ch <= CHIP_ADC_CH7) ? + (IT83XX_ADC_ADCDVSTS & (1 << adc_ch)) : + (IT83XX_ADC_ADCDVSTS2 & (1 << (adc_ch - CHIP_ADC_CH13))); +} + int adc_read_channel(enum adc_channel ch) { uint32_t events; @@ -115,13 +131,17 @@ int adc_read_channel(enum adc_channel ch) if (events & TASK_EVENT_ADC_DONE) { /* data valid of adc channel[x] */ - if (IT83XX_ADC_ADCDVSTS & (1 << adc_ch)) { + if (adc_data_valid(adc_ch)) { /* read adc raw data msb and lsb */ adc_raw_data = (*adc_ctrl_regs[adc_ch].adc_datm << 8) + *adc_ctrl_regs[adc_ch].adc_datl; /* W/C data valid flag */ - IT83XX_ADC_ADCDVSTS = (1 << adc_ch); + if (adc_ch <= CHIP_ADC_CH7) + IT83XX_ADC_ADCDVSTS = (1 << adc_ch); + else + IT83XX_ADC_ADCDVSTS2 = + (1 << (adc_ch - CHIP_ADC_CH13)); mv = adc_raw_data * adc_channels[ch].factor_mul / adc_channels[ch].factor_div + diff --git a/chip/it83xx/adc_chip.h b/chip/it83xx/adc_chip.h index 424e00c24d..e763548c1f 100644 --- a/chip/it83xx/adc_chip.h +++ b/chip/it83xx/adc_chip.h @@ -19,6 +19,23 @@ */ #define ADC_TIMEOUT_US 248 +/* List of ADC channels. */ +enum chip_adc_channel { + CHIP_ADC_CH0 = 0, + CHIP_ADC_CH1, + CHIP_ADC_CH2, + CHIP_ADC_CH3, + CHIP_ADC_CH4, + CHIP_ADC_CH5, + CHIP_ADC_CH6, + CHIP_ADC_CH7, + CHIP_ADC_CH13, + CHIP_ADC_CH14, + CHIP_ADC_CH15, + CHIP_ADC_CH16, + CHIP_ADC_COUNT, +}; + /* Data structure to define ADC channel control registers. */ struct adc_ctrl_t { volatile uint8_t *adc_ctrl; @@ -33,7 +50,7 @@ struct adc_t { int factor_mul; int factor_div; int shift; - int channel; + enum chip_adc_channel channel; }; /* diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 93417e08b9..3b3401f615 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -620,6 +620,11 @@ #define IT83XX_GPIO_GPDMRF REG8(IT83XX_GPIO_BASE+0x66) #define IT83XX_GPIO_GPDMRH REG8(IT83XX_GPIO_BASE+0x68) +#define IT83XX_GPIO_GPCRL0 REG8(IT83XX_GPIO_BASE+0x98) +#define IT83XX_GPIO_GPCRL1 REG8(IT83XX_GPIO_BASE+0x99) +#define IT83XX_GPIO_GPCRL2 REG8(IT83XX_GPIO_BASE+0x9A) +#define IT83XX_GPIO_GPCRL3 REG8(IT83XX_GPIO_BASE+0x9B) + #define IT83XX_GPIO_GRC1 REG8(IT83XX_GPIO_BASE+0xF0) #define IT83XX_GPIO_GRC2 REG8(IT83XX_GPIO_BASE+0xF1) #define IT83XX_GPIO_GRC3 REG8(IT83XX_GPIO_BASE+0xF2) @@ -867,6 +872,19 @@ enum clock_gate_offsets { #define IT83XX_ADC_VCMP2CTL REG8(IT83XX_ADC_BASE+0x4C) #define IT83XX_ADC_CMP2THRDATM REG8(IT83XX_ADC_BASE+0x4D) #define IT83XX_ADC_CMP2THRDATL REG8(IT83XX_ADC_BASE+0x4E) +#define IT83XX_ADC_VCH13CTL REG8(IT83XX_ADC_BASE+0x60) +#define IT83XX_ADC_VCH13DATM REG8(IT83XX_ADC_BASE+0x61) +#define IT83XX_ADC_VCH13DATL REG8(IT83XX_ADC_BASE+0x62) +#define IT83XX_ADC_VCH14CTL REG8(IT83XX_ADC_BASE+0x63) +#define IT83XX_ADC_VCH14DATM REG8(IT83XX_ADC_BASE+0x64) +#define IT83XX_ADC_VCH14DATL REG8(IT83XX_ADC_BASE+0x65) +#define IT83XX_ADC_VCH15CTL REG8(IT83XX_ADC_BASE+0x66) +#define IT83XX_ADC_VCH15DATM REG8(IT83XX_ADC_BASE+0x67) +#define IT83XX_ADC_VCH15DATL REG8(IT83XX_ADC_BASE+0x68) +#define IT83XX_ADC_VCH16CTL REG8(IT83XX_ADC_BASE+0x69) +#define IT83XX_ADC_VCH16DATM REG8(IT83XX_ADC_BASE+0x6A) +#define IT83XX_ADC_VCH16DATL REG8(IT83XX_ADC_BASE+0x6B) +#define IT83XX_ADC_ADCDVSTS2 REG8(IT83XX_ADC_BASE+0x6C) /* Keyboard Controller (KBC) */ #define IT83XX_KBC_BASE 0x00F01300 |