diff options
author | Vic (Chun-Ju) Yang <victoryang@chromium.org> | 2013-11-28 15:56:56 +0800 |
---|---|---|
committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2013-12-02 04:54:23 +0000 |
commit | d69d0166eebdcfe7cf2545765a65b7c22c7d197c (patch) | |
tree | 096e5dec4ad67e089b7c8613610fad752905959f | |
parent | 3f02192460f5c647f6539de161e36d5b4392567b (diff) | |
download | chrome-ec-d69d0166eebdcfe7cf2545765a65b7c22c7d197c.tar.gz |
mec1322: Add PWM driver
This adds a PWM driver, which now generates 30KHz PWM output. Note that
this is different from fan control module driver.
BUG=chrome-os-partner:24107
TEST=Set GPIO136 to PWM1. Attach logic analyzer to monitor its output.
- Set to active high and 30%, see 30% duty PWM at ~29.1KHz.
- Set to active low and 20%, see 80% duty PWM at ~29.1KHz.
BRANCH=None
Change-Id: I5f1001d5a4701e19fa87c4cabfd4ae5ae7ccb30c
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178391
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
-rw-r--r-- | chip/mec1322/build.mk | 1 | ||||
-rw-r--r-- | chip/mec1322/pwm.c | 64 | ||||
-rw-r--r-- | chip/mec1322/pwm_chip.h | 21 | ||||
-rw-r--r-- | chip/mec1322/registers.h | 8 |
4 files changed, 94 insertions, 0 deletions
diff --git a/chip/mec1322/build.mk b/chip/mec1322/build.mk index f47014ef89..3c0e4c357f 100644 --- a/chip/mec1322/build.mk +++ b/chip/mec1322/build.mk @@ -13,4 +13,5 @@ CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 # Required chip modules chip-y=clock.o gpio.o hwtimer.o system.o uart.o jtag.o +chip-$(CONFIG_PWM)+=pwm.o chip-$(CONFIG_WATCHDOG)+=watchdog.o diff --git a/chip/mec1322/pwm.c b/chip/mec1322/pwm.c new file mode 100644 index 0000000000..d66c03da05 --- /dev/null +++ b/chip/mec1322/pwm.c @@ -0,0 +1,64 @@ +/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* PWM control module for MEC1322 */ + +#include "hooks.h" +#include "pwm.h" +#include "pwm_chip.h" +#include "registers.h" +#include "util.h" + +void pwm_enable(enum pwm_channel ch, int enabled) +{ + int id = pwm_channels[ch].channel; + + if (enabled) + MEC1322_PWM_CFG(id) |= 0x1; + else + MEC1322_PWM_CFG(id) &= ~0x1; +} + +int pwm_get_enabled(enum pwm_channel ch) +{ + return MEC1322_PWM_CFG(pwm_channels[ch].channel) & 0x1; +} + +void pwm_set_duty(enum pwm_channel ch, int percent) +{ + int id = pwm_channels[ch].channel; + + if (percent < 0) + percent = 0; + else if (percent > 100) + percent = 100; + + MEC1322_PWM_ON(id) = percent; + MEC1322_PWM_OFF(id) = 100 - percent; +} + +int pwm_get_duty(enum pwm_channel ch) +{ + return MEC1322_PWM_ON(pwm_channels[ch].channel); +} + +static void pwm_configure(int ch, int active_low) +{ + MEC1322_PWM_CFG(ch) = (15 << 3) | /* Pre-divider = 16 */ + (active_low ? (1 << 2) : 0) | + (0 << 1); /* 48M clock */ +} + +static void pwm_init(void) +{ + int i; + + for (i = 0; i < PWM_CH_COUNT; ++i) { + pwm_configure(pwm_channels[i].channel, + pwm_channels[i].flags & PWM_CONFIG_ACTIVE_LOW); + pwm_set_duty(i, 0); + } +} +DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_DEFAULT); diff --git a/chip/mec1322/pwm_chip.h b/chip/mec1322/pwm_chip.h new file mode 100644 index 0000000000..7c59b1004f --- /dev/null +++ b/chip/mec1322/pwm_chip.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* MEC1322-specific PWM module for Chrome EC */ +#ifndef __CROS_EC_MEC1322_PWM_H +#define __CROS_EC_MEC1322_PWM_H + +/* Data structure to define PWM channels. */ +struct pwm_t { + /* PWM Channel ID */ + int channel; + + /* PWM channel flags. See include/pwm.h */ + uint32_t flags; +}; + +extern const struct pwm_t pwm_channels[]; + +#endif /* __CROS_EC_MEC1322_PWM_H */ diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h index 159e29c230..5d6e09685e 100644 --- a/chip/mec1322/registers.h +++ b/chip/mec1322/registers.h @@ -173,6 +173,14 @@ static inline uintptr_t gpio_port_base(int port_id) #define MEC1322_MBX_IMR REG8(MEC1322_MBX_BASE + 0xc) #define MEC1322_MBX_REG(x) REG8(MEC1322_MBX_BASE + 0x10 + (x)) + +/* PWM */ +#define MEC1322_PWM_BASE(x) (0x40005800 + (x) * 0x10) +#define MEC1322_PWM_ON(x) REG32(MEC1322_PWM_BASE(x) + 0x00) +#define MEC1322_PWM_OFF(x) REG32(MEC1322_PWM_BASE(x) + 0x04) +#define MEC1322_PWM_CFG(x) REG32(MEC1322_PWM_BASE(x) + 0x08) + + /* IRQ Numbers */ #define MEC1322_IRQ_I2C_0 0 #define MEC1322_IRQ_I2C_1 1 |