cortex-m: provide a function to set IRQ priority

On Puff we need to increase some IRQ priorities to meet strict timing
requirements. To support that, provide a function encapsulating the bit
manipulations to adjust the priority of a single IRQ and update task.c
to take advantage of it.

BUG=None
BRANCH=None
TEST=Still builds.

Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I9534f5733db48b9650a55f30e5209918a5eb24b1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2192456
Reviewed-by: Andrew McRae <amcrae@chromium.org>

5 files changed, 34 insertions, 30 deletions

diff --git a/board/puff/board.c b/board/puff/board.c
index f28d64615f..187de62cc8 100644
--- a/board/puff/board.c
+++ b/board/puff/board.c
@@ -394,16 +394,6 @@ const struct ina3221_t ina3221[] = {
 };
 const unsigned int ina3221_count = ARRAY_SIZE(ina3221);
 
-static void override_interrupt_priority(int irq, int priority)
-{
-	const uint32_t prio_shift = irq % 4 * 8 + 5;
-
-	CPU_NVIC_PRI(irq / 4) =
-		(CPU_NVIC_PRI(irq / 4) &
-		 ~(0x7 << prio_shift)) |
-		(priority << prio_shift);
-}
-
 static void board_init(void)
 {
 	uint8_t *memmap_batt_flags;
@@ -419,12 +409,12 @@ static void board_init(void)
 	 * requiring faster response must be higher priority.
 	 */
 	/* CPU_C10_GATE_L on GPIO6.7: must be ~instant for ~60us response. */
-	override_interrupt_priority(NPCX_IRQ_WKINTH_1, 1);
+	cpu_set_interrupt_priority(NPCX_IRQ_WKINTH_1, 1);
 	/*
 	 * slp_s3_interrupt (GPIOA.5 on WKINTC_0) must respond within 200us
 	 * (tPLT18); less critical than the C10 gate.
 	 */
-	override_interrupt_priority(NPCX_IRQ_WKINTC_0, 2);
+	cpu_set_interrupt_priority(NPCX_IRQ_WKINTC_0, 2);
 
 	update_port_limits();
 	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_L);
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h
index 6ff9f249be..5f7dd02801 100644
--- a/core/cortex-m/cpu.h
+++ b/core/cortex-m/cpu.h
@@ -84,4 +84,18 @@ void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length);
 /* Clean and Invalidate a single range of the D-cache */
 void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length);
 
+/* Set the priority of the given IRQ in the NVIC (0 is highest). */
+static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority)
+{
+	const uint32_t prio_shift = irq % 4 * 8 + 5;
+
+	if (priority > 7)
+		priority = 7;
+
+	CPU_NVIC_PRI(irq / 4) =
+		(CPU_NVIC_PRI(irq / 4) &
+		 ~(7 << prio_shift)) |
+		(priority << prio_shift);
+}
+
 #endif /* __CROS_EC_CPU_H */
diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c
index 98fa84452f..0cf93f2f05 100644
--- a/core/cortex-m/task.c
+++ b/core/cortex-m/task.c
@@ -850,15 +850,8 @@ static void __nvic_init_irqs(void)
 
 	/* Set priorities */
 	for (i = 0; i < exc_calls; i++) {
-		uint8_t irq = __irqprio[i].irq;
-		uint8_t prio = __irqprio[i].priority;
-		uint32_t prio_shift = irq % 4 * 8 + 5;
-		if (prio > 0x7)
-			prio = 0x7;
-		CPU_NVIC_PRI(irq / 4) =
-				(CPU_NVIC_PRI(irq / 4) &
-				 ~(0x7 << prio_shift)) |
-				(prio << prio_shift);
+		cpu_set_interrupt_priority(__irqprio[i].irq,
+					   __irqprio[i].priority);
 	}
 }
 
diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h
index ba27c1bc82..ac184090f9 100644
--- a/core/cortex-m0/cpu.h
+++ b/core/cortex-m0/cpu.h
@@ -41,4 +41,18 @@
 /* Set up the cpu to detect faults */
 void cpu_init(void);
 
+/* Set the priority of the given IRQ in the NVIC (0 is highest). */
+static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority)
+{
+	const uint32_t prio_shift = irq % 4 * 8 + 6;
+
+	if (priority > 3)
+		priority = 3;
+
+	CPU_NVIC_PRI(irq / 4) =
+		(CPU_NVIC_PRI(irq / 4) &
+		 ~(3 << prio_shift)) |
+		(priority << prio_shift);
+}
+
 #endif /* __CROS_EC_CPU_H */
diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c
index ead2bff49f..1d085431ac 100644
--- a/core/cortex-m0/task.c
+++ b/core/cortex-m0/task.c
@@ -489,15 +489,8 @@ static void __nvic_init_irqs(void)
 
 	/* Set priorities */
 	for (i = 0; i < exc_calls; i++) {
-		uint8_t irq = __irqprio[i].irq;
-		uint8_t prio = __irqprio[i].priority;
-		uint32_t prio_shift = irq % 4 * 8 + 6;
-		if (prio > 0x3)
-			prio = 0x3;
-		CPU_NVIC_PRI(irq / 4) =
-				(CPU_NVIC_PRI(irq / 4) &
-				 ~(0x3 << prio_shift)) |
-				(prio << prio_shift);
+		cpu_set_interrupt_priority(__irqprio[i].irq,
+					   __irqprio[i].priority);
 	}
 }