mchp: Add lfw/gpio.inc in chip

Add gpio.inc in chip, and update build.mk;
Delete lfw/gpio.inc under all mchp boards;

BRANCH=none
BUG=none
TEST=Build sklrvp_mchp172x.

Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: Icd98d4d93cb31f70592d6668e598fbc88e727450
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2810884
Reviewed-by: Martin Yan <Martin.Yan@microchip.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>

8 files changed, 118 insertions, 261 deletions

diff --git a/board/mchpevb1/gpio.inc b/board/mchpevb1/gpio.inc
index f3341b959a..4ba5bd15df 100644
--- a/board/mchpevb1/gpio.inc
+++ b/board/mchpevb1/gpio.inc
@@ -22,6 +22,9 @@
  * GPIO_0150 is JTAG_TMS
  */
 
+/* include common gpio.inc under chip/mchp/lfw/... */
+#include "chip/mchp/lfw/gpio.inc"
+
 #define GPIO_BOTH_EDGES_PU (GPIO_INT_BOTH | GPIO_PULL_UP)
 
 /* Only needed if CONFIG_HOSTCMD_ESPI is not set, using LPC interface to PCH */
@@ -294,23 +297,6 @@ GPIO(BOARD_VERSION1,        PIN(0114),  GPIO_INPUT)
 GPIO(BOARD_VERSION2,        PIN(0207),  GPIO_INPUT)
 GPIO(BOARD_VERSION3,        PIN(0011),  GPIO_INPUT)
 
-
-/* SPI
- * Chip select must be open drain and driven high before SPI controller
- * configuration.
- */
-/*
- * MEC1701H
- * GPIO_0055/PWM2/SHD_CS0#/RSMRST#
- * GPIO_0124/GPTP-OUT6/PVT_CS#/KSO11
- * QMSPI controller drives chip select, must be
- * configured to alternative function. See below.
- * Always use the name QMSPI_CS0 for chip select.
- * Actual GPIO could be GPIO_0055 QMSPI shared chip select or
- * GPIO_0124 private chip select.
- */
-GPIO(QMSPI_CS0,		PIN(055),  GPIO_ODR_HIGH)
-
 /*
  * MEC1701H GP-SPI0 chip select is GPIO_0003
  * It is used as GPIO output. GPSPI chip level
@@ -341,14 +327,6 @@ GPIO(TFDP_DATA,		PIN(0171), GPIO_INPUT)
 #define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
 #define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
 
-
-/*
- * GPIO_0104(UART0_TX) Func1
- * GPIO_0105(UART0_RX) Func1
- * Bank 2 bits[4:5]
- */
-ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
-
 /* KB pins */
 /*
  * MEC1704H (144 pin package)
@@ -413,25 +391,6 @@ ALTERNATE(PIN_MASK(1, 0xf000000), 2, MODULE_LPC, 0)
  * Function 1, Bank 1 bit[20] */
 ALTERNATE(PIN_MASK(1, 0x100000), 1, MODULE_LPC, GPIO_PULL_UP)
 
-/* MECC card SPI flash is connected to QMSPI Shared Port
- * Also, MEC1701H Private SPI Port (Port 1) has pins multiplexed
- * with KSO pins used in key scan!
- * QMSPI Shared SPI Port (Port 0)
- * NOTE: QMSPI Shared SPI Port pins are on VTR2
- */
-/*
- * MEC1701H SHD SPI is connected to QMSPI controller.
- * QMSPI drives chip select. SHD_CS0#(GPIO_0055) must be set
- * to alternate function 2 and GPIO_ODR_HIGH.
- * GPIO_0055 Function 2, Bank 1 bit[13]
- */
-ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
-/* SHD_CLK - GPIO_0056 Function 2, Bank 1 bit[14] */
-ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
-/* MOSI(SHD_IO0) - GPIO_0223 Function 2, Bank 4 bit[19] */
-/* MISO(SHD_IO1) - GPIO_0224 Function 2, Bank 4 bit[20] */
-ALTERNATE(PIN_MASK(4, 0x180000), 2, MODULE_SPI_FLASH, 0)
-
 /*
  * MEC1701H GP-SPI0 Master
  * SPI0_CS# = GPIO_0003 Func 0(GPIO) Bank 0, bit 3
diff --git a/board/mchpevb1/lfw/gpio.inc b/board/mchpevb1/lfw/gpio.inc
deleted file mode 100644
index f4142d3c29..0000000000
--- a/board/mchpevb1/lfw/gpio.inc
+++ /dev/null
@@ -1,43 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Minimal set of GPIOs needed for LFW loader
- */
-
-/*
- * MEC1701H GPIO_0055/PWM2/SHD_CS0#/RSMRST#
- * MEC1701H QMSPI controller drives chip select, must be
- * configured to alternative function. See below.
- * GPIO_SHD_CS0 is used in board level spi_devices[] table
- */
-GPIO(QMSPI_CS0,	PIN(055),  GPIO_ODR_HIGH)
-
-
-/* Alternate functions GPIO definition */
-
-/*
- * UART
- * GPIO_0104(UART0_TX) Func1
- * GPIO_0105(UART0_RX) Func1
- * Bank 2 bits[4:5]
-*/
-ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
-
-/* SPI pins */
-/*
- * MEC1701H SHD SPI is connected to QMSPI controller.
- * QMSPI drives chip select. SHD_CS0#(GPIO_0055) must be set
- * to alternate function 2 and GPIO_ODR_HIGH.
- * GPIO_0055 Function 2, Bank 1 bit[13]
- */
-ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
-/* SHD_CLK - GPIO_0056 Function 2, Bank 1 bit[14] */
-ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
-/* MOSI(SHD_IO0) - GPIO_0223 Function 2, Bank 4 bit[19] */
-/* MISO(SHD_IO1) - GPIO_0224 Function 2, Bank 4 bit[20] */
-ALTERNATE(PIN_MASK(4, 0x180000), 2, MODULE_SPI_FLASH, 0)
-
-
diff --git a/board/reef_mchp/gpio.inc b/board/reef_mchp/gpio.inc
index baaf36330e..ff98b4c1b9 100644
--- a/board/reef_mchp/gpio.inc
+++ b/board/reef_mchp/gpio.inc
@@ -8,6 +8,9 @@
 /* Declare symbolic names for all the GPIOs that we care about.
  * Note: Those with interrupt handlers must be declared first. */
 
+/* include common gpio.inc under chip/mchp/lfw/... */
+#include "chip/mchp/lfw/gpio.inc"
+
 /* MEC1701H GPIO_0105/UART0_RX OK */
 GPIO_INT(UART0_RX, PIN(0105), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, \
 	 uart_deepsleep_interrupt)
@@ -168,34 +171,9 @@ GPIO(BAT_LED_BLUE,		PIN(0153), GPIO_OUT_HIGH)
 GPIO(BAT_LED_AMBER,		PIN(0226), GPIO_OUT_HIGH)
 
 /*
- * MEC1701H
- * GPIO_0055/PWM2/SHD_CS0#/RSMRST#
- * GPIO_0124/GPTP-OUT6/PVT_CS#/KSO11
- * QMSPI controller drives chip select, must be
- * configured to alternative function. See below.
- * Always use the name QMSPI_CS0 for chip select.
- * Actual GPIO could be GPIO_0055 QMSPI shared chip select or
- * GPIO_0124 private chip select.
- */
-GPIO(QMSPI_CS0,	PIN(055),  GPIO_ODR_HIGH)
-
-/*
  * Alternate function pins
  */
 
-/*
- * MEC1701H SHD SPI is connected to QMSPI controller.
- * QMSPI drives chip select. SHD_CS0#(GPIO_0055) must be set
- * to alternate function 2 and GPIO_ODR_HIGH.
- * GPIO_0055 Function 2, Bank 1 bit[13]
- */
-ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
-/* SHD_CLK - GPIO_0056 Function 2, Bank 1 bit[14] */
-ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
-/* MOSI(SHD_IO0) - GPIO_0223 Function 2, Bank 4 bit[19] */
-/* MISO(SHD_IO1) - GPIO_0224 Function 2, Bank 4 bit[20] */
-ALTERNATE(PIN_MASK(4, 0x180000), 2, MODULE_SPI_FLASH, 0)
-
 /* MEC1701H LPC all alternate function 1
  *			bank	bit
  * GPIO061 LPCPD#	1	17
@@ -291,13 +269,6 @@ ALTERNATE(PIN_MASK(3, 0x00003001), 1, MODULE_I2C, 0)
 //ALTERNATE(PIN_MASK(0, 0x00000006), 1, MODULE_PWM, 0)
 
 /*
- * GPIO_0104(UART0_TX) Func1
- * GPIO_0105(UART0_RX) Func1
- * Bank 2 bits[4:5]
- */
-ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
-
-/*
  * MCHP TFDP alternate function configuration
  * GPIO 0170 = clock, 0171 = data both function 1
  * Port = 3 bits[24:25]
diff --git a/board/reef_mchp/lfw/gpio.inc b/board/reef_mchp/lfw/gpio.inc
deleted file mode 100644
index f4142d3c29..0000000000
--- a/board/reef_mchp/lfw/gpio.inc
+++ /dev/null
@@ -1,43 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Minimal set of GPIOs needed for LFW loader
- */
-
-/*
- * MEC1701H GPIO_0055/PWM2/SHD_CS0#/RSMRST#
- * MEC1701H QMSPI controller drives chip select, must be
- * configured to alternative function. See below.
- * GPIO_SHD_CS0 is used in board level spi_devices[] table
- */
-GPIO(QMSPI_CS0,	PIN(055),  GPIO_ODR_HIGH)
-
-
-/* Alternate functions GPIO definition */
-
-/*
- * UART
- * GPIO_0104(UART0_TX) Func1
- * GPIO_0105(UART0_RX) Func1
- * Bank 2 bits[4:5]
-*/
-ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
-
-/* SPI pins */
-/*
- * MEC1701H SHD SPI is connected to QMSPI controller.
- * QMSPI drives chip select. SHD_CS0#(GPIO_0055) must be set
- * to alternate function 2 and GPIO_ODR_HIGH.
- * GPIO_0055 Function 2, Bank 1 bit[13]
- */
-ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
-/* SHD_CLK - GPIO_0056 Function 2, Bank 1 bit[14] */
-ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
-/* MOSI(SHD_IO0) - GPIO_0223 Function 2, Bank 4 bit[19] */
-/* MISO(SHD_IO1) - GPIO_0224 Function 2, Bank 4 bit[20] */
-ALTERNATE(PIN_MASK(4, 0x180000), 2, MODULE_SPI_FLASH, 0)
-
-
diff --git a/board/sklrvp_mchp/gpio.inc b/board/sklrvp_mchp/gpio.inc
index 164d2f16f4..9f9dde51f9 100644
--- a/board/sklrvp_mchp/gpio.inc
+++ b/board/sklrvp_mchp/gpio.inc
@@ -41,6 +41,9 @@
  * MEC1521H-SZ: 0213, 0211, 0212
  */
 
+/* include common gpio.inc under chip/mchp/lfw/... */
+#include "chip/mchp/lfw/gpio.inc"
+
 #define GPIO_BOTH_EDGES_PU (GPIO_INT_BOTH | GPIO_PULL_UP)
 #define GPIO_KB_OUTPUT_COL2 (GPIO_OUT_LOW)
 
@@ -197,26 +200,7 @@ GPIO(BOARD_VERSION1,        PIN(0114),  GPIO_INPUT)
 GPIO(BOARD_VERSION2,        PIN(0207),  GPIO_INPUT)
 GPIO(BOARD_VERSION3,        PIN(0011),  GPIO_INPUT)
 
-
-/* SPI
- * Chip select must be open drain and driven high before SPI controller
- * configuration.
- */
-/*
- * MEC1521H-SZ
- * GPIO_0055/PWM2/SHD_CS0#/RSMRST#
- * GPIO_0056/PWM3/SHD_CLK
- * GPIO_0223/SHD_IO0
- * GPIO_0224/GPTP_IN0/SHD_IO1
- * GPIO_0227/SHD_IO2[PWRGD_STRAP]
- * GPIO_0016/GPTP_IN1/SHD_IO3/ICT3(DSW_PWROK)
- *
- * QMSPI controller drives chip select, must be
- * configured to alternative function. See below.
- * Always use the name QMSPI_CS0 for chip select.
- */
-GPIO(QMSPI_CS0,		PIN(055),  GPIO_ODR_HIGH)
-
+/* For LEDs */
 GPIO(BAT_LED_GREEN_L,	PIN(0156), GPIO_OUT_HIGH)
 GPIO(AC_LED_GREEN_L,	PIN(0157), GPIO_OUT_HIGH)
 
@@ -235,14 +219,6 @@ GPIO(EC_SPI_OE_N, PIN(0253), GPIO_OUT_LOW)
 ALTERNATE(PIN_MASK(3, 0x200000), 1, MODULE_PMU, 0)
 #endif
 
-/*
- * UART0
- * GPIO_0105 Func 1 = UART_RX
- * GPIO_0104 Func 1 = UART_TX
- * Bank 2 bits[5:4]
- */
-ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
-
 /* KB pins */
 /*
  * MEC1521H-SZ (144 pin package)
@@ -305,35 +281,6 @@ ALTERNATE(PIN_MASK(0, 0x07C38000), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
  */
 ALTERNATE(PIN_MASK(1, 0x0F6A0000), 1, MODULE_LPC, 0)
 
-/* MECC card SPI flash is connected to QMSPI Shared Port
- * Also, MEC1521H-SZ Private SPI Port (Port 1) has pins multiplexed
- * with KSO pins used in key scan!
- * QMSPI Shared SPI Port (Port 0)
- * NOTE: QMSPI Shared SPI Port pins are on VTR2
- */
-/*
- * MEC1521H-SZ MECC board SPI flash is connected to MEC1521H-SZ shared
- * SPI port. SHD_nCS is the chip select signal connected to
- * GPIO_0055(SHD_CS0#) pin. MECC board has 10K pulls to +3.3V on all
- * the board SPI flash signals. MEC152x SHD SPI signals are on the chip's
- * VTR2 rail. If VTR2 is connected to 1.8V there could be back drive issues.
- * We must set the respective GPIO's to their shared SPI alternate functions.
- * Only enable CS0#, CLK, IO0, and IO1 as EC code does not use quad mode.
- * NOTE 1: SHD_IO2 is also used a Boot-ROM PWRGD_STRAP.
- * NOTE 2: Be very careful re-using SHD_IO2 and SHD_IO3 for other functions.
- * SHD_CS0# will be set to open drain drive high.
- * SHD_CS0# = GPIO_0055(Bank 1, bit[13]) Func2
- * SHD_CLK  = GPIO_0056(Bank 1, bit[14]) Func2
- * SHD_IO0  = GPIO_0223(Bank 4, bit[19]) Func1
- * SHD_IO1  = GPIO_0224(Bank 4, bit[20]) Func2
- * SHD_IO2  = GPIO_0227(Bank 4, bit[23]) Func1
- * SHD_IO3  = GPIO_0016(Bank 0, bit[14]) Func2
- */
-ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
-ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
-ALTERNATE(PIN_MASK(4, 0x00080000), 1, MODULE_SPI_FLASH, 0)
-ALTERNATE(PIN_MASK(4, 0x00100000), 2, MODULE_SPI_FLASH, 0)
-
 /* I2C pins */
 /* MEC1521H-SZ does not implement I2C08 pins
  * Configure I2C00-05 as I2C alternate function
diff --git a/board/sklrvp_mchp/lfw/gpio.inc b/board/sklrvp_mchp/lfw/gpio.inc
deleted file mode 100644
index e969e4d09c..0000000000
--- a/board/sklrvp_mchp/lfw/gpio.inc
+++ /dev/null
@@ -1,41 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Minimal set of GPIOs needed for LFW loader
- */
-
-/*
- * MEC1701H GPIO_0055/PWM2/SHD_CS0#/RSMRST#
- * MEC1701H QMSPI controller drives chip select, must be
- * configured to alternative function. See below.
- * GPIO_SHD_CS0 is used in board level spi_devices[] table
- */
-GPIO(QMSPI_CS0,	PIN(055),  GPIO_ODR_HIGH)
-
-
-/* Alternate functions GPIO definition */
-
-/*
- * UART0
- * GPIO_0105 Func 1 = UART_RX
- * GPIO_0104 Func 1 = UART_TX
- * Bank 2 bits[5:4]
- */
-ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
-
-/* SPI pins */
-/*
- * MEC1701H SHD SPI is connected to QMSPI controller.
- * QMSPI drives chip select. SHD_CS0#(GPIO_0055) must be set
- * to alternate function 2 and GPIO_ODR_HIGH.
- * GPIO_0055 Function 2, Bank 1 bit[13]
- */
-ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
-/* SHD_CLK - GPIO_0056 Function 2, Bank 1 bit[14] */
-ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
-/* MOSI(SHD_IO0) - GPIO_0223 Function 2, Bank 4 bit[19] */
-/* MISO(SHD_IO1) - GPIO_0224 Function 2, Bank 4 bit[20] */
-ALTERNATE(PIN_MASK(4, 0x180000), 2, MODULE_SPI_FLASH, 0)
diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk
index 506d0d3470..262499f3e5 100644
--- a/chip/mchp/build.mk
+++ b/chip/mchp/build.mk
@@ -91,7 +91,7 @@ objs_lfw += $(out)/RW/common/version.o
 dirs-y+=chip/$(CHIP)/lfw
 
 # objs with -lfw suffix are to include lfw's gpio
-$(out)/RW/%-lfw.o: private CC+=-I$(BDIR)/lfw -DLFW=$(EMPTY)
+$(out)/RW/%-lfw.o: private CC+=-Ichip/mchp/lfw -DLFW=$(EMPTY)
 # Remove the lto flag for the loader.  It actually causes it to bloat in size.
 ifeq ($(CONFIG_LTO),y)
 $(out)/RW/%-lfw.o: private CFLAGS_CPU := $(filter-out -flto, $(CFLAGS_CPU))
diff --git a/chip/mchp/lfw/gpio.inc b/chip/mchp/lfw/gpio.inc
new file mode 100644
index 0000000000..41321c8b0c
--- /dev/null
+++ b/chip/mchp/lfw/gpio.inc
@@ -0,0 +1,107 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Common GPIOs needed for LFW loader and main process FW
+ */
+
+/* SPI
+ * External SPI chip select must be open drain and driven high or
+ * internal SPI chip select must be push-pull and driven high before
+ * SPI controller configuration.
+ * QMSPI external Shared CS0# is GPIO_0055
+ * QMSPI internal CS0# is GPIO_0116
+ */
+#if defined(CHIP_VARIANT_MEC1727SZ)
+GPIO(QMSPI_CS0, PIN(0116), GPIO_PULL_UP | GPIO_HIGH)
+#else
+GPIO(QMSPI_CS0, PIN(055), GPIO_ODR_HIGH)
+#endif
+
+/* Boot-ROM loads from external or internal SPI flash.
+ * There are two external ports: shared(default) and private.
+ * NOTE: QMSPI Shared SPI Port pins are on VTR2
+ * SHD_CS0# = GPIO 0055 Func 2 bank 1 b[13]
+ * SHD_CLK  = GPIO 0056 Func 2 bank 1 b[14]
+ * SHD_IO0  = GPIO 0223 Func 1 bank 4 b[19]
+ * SHD_IO1  = GPIO 0224 Func 2 bank 4 b[20]
+ * Not using IO2 and IO2 as data
+ * SHD_IO2  = GPIO 0227 Func 1 bank 4 b[23]
+ * SHD_IO3  = GPIO 0016 Func 2 bank 0 b[14]
+ * MEC1727 variants load from internal 512KB SPI flash(internal only pins)
+ * INT_CS# = GPIO 0116 Func 1 bank 2 14
+ * INT_SCK = GPIO 0117 Func 1 bank 2 15
+ * INT_IO0 = GPIO 0074 Func 1 bank 1 28
+ * INT_IO1 = GPIO 0075 Func 1 bank 1 29
+ * INT_WP# = GPIO 0076 Func 0 for WP# control
+ * Internal flash HOLD# connected to VTR1 rail.
+ */
+#if defined(CHIP_VARIANT_MEC1727SZ)
+/* MEC1727 variants have internal SPI flash on internal only pins */
+ALTERNATE(PIN_MASK(2, 0x4000), 2, MODULE_SPI_FLASH, GPIO_PULL_UP)
+ALTERNATE(PIN_MASK(2, 0x8000), 2, MODULE_SPI_FLASH, 0)
+ALTERNATE(PIN_MASK(1, 0x30000000), 1, MODULE_SPI_FLASH, 0)
+#else
+/* external SPI flash on QMSPI SHD_xx pins */
+ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
+ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
+ALTERNATE(PIN_MASK(4, 0x080000), 1, MODULE_SPI_FLASH, 0)
+ALTERNATE(PIN_MASK(4, 0x100000), 2, MODULE_SPI_FLASH, 0)
+#endif
+
+/* UART
+ * Per CONFIG_UART_CONSOLE and chip to configure UART pins
+ */
+#if CONFIG_UART_CONSOLE == 0
+/* select UART0 */
+/* MEC170X, MEC152X and MEC172X support same UART0 pins and ALT function */
+/*
+ * UART0
+ * GPIO_0105 Func 1 = UART_RX
+ * GPIO_0104 Func 1 = UART_TX
+ * Bank 2 bits[5:4]
+ */
+ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
+
+#elif CONFIG_UART_CONSOLE == 1
+/* select UART1 */
+/* MEC170X, MEC152X and MEC172X support same UART1 pins
+ * but ALT function 2 on MEC170X, function 1 on others
+ */
+#if defined(CHIP_FAMILY_MEC170X)
+/*
+ * UART1
+ * GPIO_0171 Func 2 = UART_RX
+ * GPIO_0170 Func 2 = UART_TX
+ * Bank 3 bits[25:24]
+ */
+ALTERNATE(PIN_MASK(3, 0x03000000), 2, MODULE_UART, 0)
+
+#else
+/*
+ * UART1
+ * GPIO_0171 Func 1 = UART_RX
+ * GPIO_0170 Func 1 = UART_TX
+ * Bank 3 bits[25:24]
+ */
+ALTERNATE(PIN_MASK(3, 0x03000000), 1, MODULE_UART, 0)
+
+#endif /* defined(CHIP_FAMILY_MEC170X) */
+
+#else
+/* select UART2 */
+/* only MEC152X supports UART2 pins */
+#if defined(CHIP_FAMILY_MEC152X)
+/*
+ * UART2
+ * GPIO_0145 Func 2 = UART_RX
+ * GPIO_0146 Func 2 = UART_TX
+ * Bank 3 bits[6:5]
+ */
+ALTERNATE(PIN_MASK(3, 0x60), 2, MODULE_UART, 0)
+
+#endif /* defined(CHIP_FAMILY_MEC152X) */
+
+#endif /* CONFIG_UART_CONSOLE == 0 */