diff options
| author | martin yan <martin.yan@microchip.corp-partner.google.com> | 2022-01-28 13:47:52 -0500 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2022-02-01 19:58:58 +0000 |
| commit | a1d1af858da7621fb1cd840afc33d935d07af5f2 (patch) | |
| tree | 7a1cf28e6eefbbcd6ba70d27f0ce02b7993b924b | |
| parent | 8367fb87a332878a2c501336e1a8b50c3e908361 (diff) | |
| download | chrome-ec-a1d1af858da7621fb1cd840afc33d935d07af5f2.tar.gz | |
mchp: Fix MEC172x RO_FRID wrong area_offset in SPI image
Update config_flash_layout.h to fix RO_FRID wrong area_offset
in SPI image, this offset is used in CPFE process to validate FWID
refer to https://chromium-review.googlesource.com/c/chromiumos/overlays
/chromiumos-overlay/+/3282675
BUG=none
BRANCH=none
TEST=Verified in adlrvpp_mchp1727 board ec.bin
Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: Ic0acd9b8a202d6c99f8b04dc429fa5a2909099c5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3425157
Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
| -rw-r--r-- | chip/mchp/config_flash_layout.h | 24 |
1 files changed, 22 insertions, 2 deletions
diff --git a/chip/mchp/config_flash_layout.h b/chip/mchp/config_flash_layout.h index d423ac0238..caa1e204e0 100644 --- a/chip/mchp/config_flash_layout.h +++ b/chip/mchp/config_flash_layout.h @@ -103,13 +103,33 @@ * NOTE: EC_RO and EC_RW must start at CONFIG_FLASH_ERASE_SIZE or * greater aligned boundaries. */ -#define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000 + #define CONFIG_RW_BOOT_HEADER_STORAGE_OFF 0 #if defined(CHIP_FAMILY_MEC172X) -#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0xc0 +/* + * Changed to 0x140 original 0xc0 which is incorrect + * Python SPI image generator is locating header at offset 0x100 which is + * in first 4KB. We moved header into first 4KB to free up the 0x140 (320) + * bytes of code image space. Layout is: + * SPI Offset: + * 0x0 - 0x3 = Boot-ROM TAG + * 0x4 - 0xff = 0xFF padding + * 0x100 - 0x23F = Boot-ROM Header must be on >= 0x100 boundary + * This header points to LFW at 0x1000 + * 0x240 - 0xfff = 0xFF padding + * 0x1000 - 0x1fff = 4KB Little Firmware loaded by Boot-ROM into first 4KB + * of CODE SRAM. + * 0x2000 - 0x3ffff = EC_RO padded with 0xFF + * 0x40000 - 0x7ffff = EC_RW padded with 0xFF + * To EC the "header" is one 4KB chunk at offset 0 + */ +#define CONFIG_BOOT_HEADER_STORAGE_OFF 0 +#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x1000 #elif defined(CHIP_FAMILY_MEC152X) +#define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000 #define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x140 #elif defined(CHIP_FAMILY_MEC170X) +#define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000 #define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x80 #else #error "FORCED BUILD ERROR: CHIP_FAMILY_xxxx not set or invalid" |