diff options
| author | Jes B. Klinke <jbk@chromium.org> | 2021-12-28 10:44:40 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2022-02-03 22:03:46 +0000 |
| commit | c0c728d22621d6364d4bd62053adce4acc9424aa (patch) | |
| tree | ecc6aa7253374bb031de54b71c9ca0033e6e6267 | |
| parent | 1575a36fe1239b24f2bc3d5a42de8a66a4b18cdb (diff) | |
| download | chrome-ec-c0c728d22621d6364d4bd62053adce4acc9424aa.tar.gz | |
chip/stm32/registers-stm32l5.h: Add register bank F, G
It turns out that the L5xx series has two more register banks on top
of the L4xx code that I originally copied from.
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
BUG=b:192262089
TEST=Observe gpioset work on additional pins on HyperDebug
BRANCH=none
Change-Id: I302237ace0d8bcf5e96450e226d3d557d5a1d7fd
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3359922
Tested-by: Jes Klinke <jbk@chromium.org>
Auto-Submit: Jes Klinke <jbk@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
| -rw-r--r-- | chip/stm32/registers-stm32l5.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/chip/stm32/registers-stm32l5.h b/chip/stm32/registers-stm32l5.h index 08b3bc67b3..1c8904dd26 100644 --- a/chip/stm32/registers-stm32l5.h +++ b/chip/stm32/registers-stm32l5.h @@ -369,7 +369,8 @@ #define STM32_RCC_AHB2ENR_GPIOMASK \ (STM32_RCC_AHB2ENR_GPIOAEN | STM32_RCC_AHB2ENR_GPIOBEN | \ STM32_RCC_AHB2ENR_GPIOCEN | STM32_RCC_AHB2ENR_GPIODEN | \ - STM32_RCC_AHB2ENR_GPIOEEN | STM32_RCC_AHB2ENR_GPIOHEN) + STM32_RCC_AHB2ENR_GPIOEEN | STM32_RCC_AHB2ENR_GPIOFEN | \ + STM32_RCC_AHB2ENR_GPIOGEN | STM32_RCC_AHB2ENR_GPIOHEN) #define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << STM32_RCC_CR_MSIRANGE_POS) #define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) #define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) |