zephyr: mchp: Add cros_system driver

Add cros_system driver and related configs

BUG=none
BRANCH=main
TEST=zmake testall

Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: I58cb735adfe6f631c48d14eeccfcba9e110d7942
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3390288
Reviewed-by: Yuval Peress <peress@google.com>

5 files changed, 306 insertions, 0 deletions

diff --git a/zephyr/drivers/cros_system/CMakeLists.txt b/zephyr/drivers/cros_system/CMakeLists.txt
index 733b8be450..b0d3730cbc 100644
--- a/zephyr/drivers/cros_system/CMakeLists.txt
+++ b/zephyr/drivers/cros_system/CMakeLists.txt
@@ -4,3 +4,4 @@
 
 zephyr_library_sources_ifdef(CONFIG_CROS_SYSTEM_IT8XXX2	cros_system_it8xxx2.c)
 zephyr_library_sources_ifdef(CONFIG_CROS_SYSTEM_NPCX	cros_system_npcx.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_SYSTEM_XEC	cros_system_xec.c)
diff --git a/zephyr/drivers/cros_system/Kconfig b/zephyr/drivers/cros_system/Kconfig
index c5d98b6081..3f58f0eb21 100644
--- a/zephyr/drivers/cros_system/Kconfig
+++ b/zephyr/drivers/cros_system/Kconfig
@@ -45,3 +45,26 @@ config CROS_SYSTEM_IT8XXX2_INIT_PRIORITY
 	  CONFIG_PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY.
 
 endif # CROS_SYSTEM_IT8XXX2
+
+menuconfig CROS_SYSTEM_XEC
+	bool "Microchip XEC cros system driver"
+	depends on SOC_FAMILY_MEC
+	default y
+	help
+	  This option enables the cros system driver for the MCHP XEC family of
+	  processors. Currently, Zephyr doesn't provide the system related API.
+	  The cros system driver provides the low-level driver related to
+	  chromium ec system functionality.
+
+if CROS_SYSTEM_XEC
+
+config CROS_SYSTEM_XEC_INIT_PRIORITY
+	int "cros_system MEC initialization priority"
+	default 10
+	help
+	  This sets the MEC cros_system driver initialization priority.
+	  The cros_system driver provides access to the MEC reset cause
+	  and must be higher priority than
+	  CONFIG_PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY.
+
+endif # CONFIG_CROS_SYSTEM_XEC
diff --git a/zephyr/drivers/cros_system/cros_system_xec.c b/zephyr/drivers/cros_system/cros_system_xec.c
new file mode 100644
index 0000000000..0fce933b98
--- /dev/null
+++ b/zephyr/drivers/cros_system/cros_system_xec.c
@@ -0,0 +1,171 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
+#include <drivers/cros_system.h>
+#include <drivers/gpio.h>
+#include <drivers/watchdog.h>
+#include <logging/log.h>
+#include <soc.h>
+#include <soc/microchip_xec/reg_def_cros.h>
+#include <sys/util.h>
+
+#include "gpio.h"
+#include "system.h"
+#include "system_chip.h"
+
+LOG_MODULE_REGISTER(cros_system, LOG_LEVEL_ERR);
+
+/* Driver config */
+struct cros_system_xec_config {
+	/* hardware module base address */
+	uintptr_t base_pcr;
+	uintptr_t base_vbr;
+	uintptr_t base_wdog;
+};
+
+/* Driver data */
+struct cros_system_xec_data {
+	int reset; /* reset cause */
+};
+
+/* Driver convenience defines */
+#define DRV_CONFIG(dev) ((const struct cros_system_xec_config *)(dev)->config)
+#define DRV_DATA(dev) ((struct cros_system_xec_data *)(dev)->data)
+
+#define HAL_PCR_INST(dev) (struct pcr_regs *)(DRV_CONFIG(dev)->base_pcr)
+#define HAL_VBATR_INST(dev) (struct vbatr_regs *)(DRV_CONFIG(dev)->base_vbr)
+#define HAL_WDOG_INST(dev) (struct wdt_regs *)(DRV_CONFIG(dev)->base_wdog)
+
+/* Get saved reset flag address in battery-backed ram */
+#define BBRAM_SAVED_RESET_FLAG_ADDR                         \
+	(DT_REG_ADDR(DT_INST(0, microchip_xec_bbram)) + \
+	 DT_PROP(DT_PATH(named_bbram_regions, saved_reset_flags), offset))
+
+/* Soc specific system local functions */
+static int system_xec_watchdog_stop(void)
+{
+	if (IS_ENABLED(CONFIG_WATCHDOG)) {
+		const struct device *wdt_dev = DEVICE_DT_GET(
+				DT_NODELABEL(wdog));
+		if (!device_is_ready(wdt_dev)) {
+			LOG_ERR("Error: device %s is not ready", wdt_dev->name);
+			return -ENODEV;
+		}
+
+		wdt_disable(wdt_dev);
+	}
+
+	return 0;
+}
+
+static const char *cros_system_xec_get_chip_vendor(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return "MCHP";
+}
+
+/* TODO - return specific chip name such as MEC1727 or MEC1723 */
+static const char *cros_system_xec_get_chip_name(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return "MEC172X";
+}
+
+/* TODO return chip revision from HW as an ASCII string */
+static const char *cros_system_xec_get_chip_revision(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return "B0";
+}
+
+static int cros_system_xec_get_reset_cause(const struct device *dev)
+{
+	struct cros_system_xec_data *data = DRV_DATA(dev);
+
+	return data->reset;
+}
+
+/* MCHP TODO check and verify this logic for all corner cases:
+ * Someone doing ARM Vector Reset insead of SYSRESETREQ or HW reset.
+ * Does NRESETIN# status get set also on power on from no power state?
+ */
+static int cros_system_xec_init(const struct device *dev)
+{
+	struct vbatr_regs *vbr = HAL_VBATR_INST(dev);
+	struct cros_system_xec_data *data = DRV_DATA(dev);
+	uint32_t pfsr = vbr->PFRS;
+
+	if (IS_BIT_SET(pfsr, MCHP_VBATR_PFRS_WDT_POS)) {
+		data->reset = WATCHDOG_RST;
+		vbr->PFRS = BIT(MCHP_VBATR_PFRS_WDT_POS);
+	} else if (IS_BIT_SET(pfsr, MCHP_VBATR_PFRS_SYSRESETREQ_POS)) {
+		data->reset = DEBUG_RST;
+		vbr->PFRS = BIT(MCHP_VBATR_PFRS_SYSRESETREQ_POS);
+	} else if (IS_BIT_SET(pfsr, MCHP_VBATR_PFRS_RESETI_POS)) {
+		data->reset = VCC1_RST_PIN;
+	} else {
+		data->reset = POWERUP;
+	}
+
+	return 0;
+}
+
+noreturn static int cros_system_xec_soc_reset(const struct device *dev)
+{
+	struct pcr_regs *const pcr = HAL_PCR_INST(dev);
+
+	/* Disable interrupts to avoid task swaps during reboot */
+	interrupt_disable_all();
+
+	/* Trigger chip reset */
+	pcr->SYS_RST |= MCHP_PCR_SYS_RESET_NOW;
+	/* Wait for the soc reset */
+	while (1)
+		;
+	/* should never return */
+	/* return 0; */
+}
+
+static int cros_system_xec_hibernate(const struct device *dev,
+				     uint32_t seconds, uint32_t microseconds)
+{
+	/* Disable interrupt first */
+	interrupt_disable_all();
+
+	/* Stop the watchdog */
+	system_xec_watchdog_stop();
+
+	/* Enter hibernate mode */
+
+	/* MCHP TODO */
+
+	return 0;
+}
+
+static struct cros_system_xec_data cros_system_xec_dev_data;
+
+static const struct cros_system_xec_config cros_system_dev_cfg = {
+	.base_pcr = DT_REG_ADDR_BY_NAME(DT_INST(0, microchip_xec_pcr), pcrr),
+	.base_vbr = DT_REG_ADDR_BY_NAME(DT_INST(0, microchip_xec_pcr), vbatr),
+	.base_wdog = DT_REG_ADDR(DT_INST(0, microchip_xec_watchdog)),
+};
+
+static const struct cros_system_driver_api cros_system_driver_xec_api = {
+	.get_reset_cause = cros_system_xec_get_reset_cause,
+	.soc_reset = cros_system_xec_soc_reset,
+	.hibernate = cros_system_xec_hibernate,
+	.chip_vendor = cros_system_xec_get_chip_vendor,
+	.chip_name = cros_system_xec_get_chip_name,
+	.chip_revision = cros_system_xec_get_chip_revision,
+};
+
+DEVICE_DEFINE(cros_system_xec_0, "CROS_SYSTEM", cros_system_xec_init, NULL,
+	      &cros_system_xec_dev_data, &cros_system_dev_cfg, PRE_KERNEL_1,
+	      CONFIG_CROS_SYSTEM_XEC_INIT_PRIORITY,
+	      &cros_system_driver_xec_api);
diff --git a/zephyr/include/cros/microchip/mec1727.dtsi b/zephyr/include/cros/microchip/mec1727.dtsi
new file mode 100644
index 0000000000..b388f456d2
--- /dev/null
+++ b/zephyr/include/cros/microchip/mec1727.dtsi
@@ -0,0 +1,17 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/microchip/mec172x.dtsi>
+
+/ {
+
+	soc {
+
+	};
+
+};
+
diff --git a/zephyr/include/cros/microchip/mec172x.dtsi b/zephyr/include/cros/microchip/mec172x.dtsi
new file mode 100644
index 0000000000..42e1859ef8
--- /dev/null
+++ b/zephyr/include/cros/microchip/mec172x.dtsi
@@ -0,0 +1,94 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/binman.dtsi>
+#include <microchip/mec172xnsz.dtsi>
+
+/ {
+	chosen {
+		cros-ec,adc = &adc0;
+		cros-ec,bbram = &bbram;
+		cros-ec,espi = &espi0;
+		cros-ec,flash = &fiu0;
+		cros-ec,raw-kb = &cros_kb_raw;
+		cros-ec,watchdog = &wdog;
+		cros,rtc = &crtc;
+	};
+
+	named-bbram-regions {
+		compatible = "named-bbram-regions";
+
+		scratchpad {
+			offset = <0x00>;
+			size = <0x04>;
+		};
+		saved-reset-flags {
+			offset = <0x04>;
+			size = <0x04>;
+		};
+		wake {
+			offset = <0x08>;
+			size = <0x04>;
+		};
+		pd0 {
+			offset = <0x0c>;
+			size = <0x01>;
+		};
+		pd1 {
+			offset = <0x0d>;
+			size = <0x01>;
+		};
+		try_slot {
+			offset = <0x0e>;
+			size = <0x01>;
+		};
+		pd2 {
+			offset = <0x0f>;
+			size = <0x01>;
+		};
+		ramlog {
+			offset = <0x20>;
+			size = <0x01>;
+		};
+		panic_flags {
+			offset = <0x23>;
+			size = <0x01>;
+		};
+		panic_bkup {
+			offset = <0x24>;
+			size = <0x1c>;
+		};
+		lct_time {
+			offset = <0x40>;
+			size = <0x04>;
+		};
+	};
+
+	fiu0: cros-flash{
+		compatible = "microchip,xec-cros-flash";
+		label = "INTERNAL_FLASH";
+	};
+
+/*
+ *	power-states {
+ *	suspend_to_idle_instant: suspend_to_idle_instant {
+ *	compatible = "zephyr,power-state";
+ *	power-state-name = "suspend-to-idle";
+ *	substate-id = <0>;
+ *	min-residency-us = <500>;
+ *	};
+ *
+ *	suspend_to_idle_normal: suspend_to_idle_normal {
+ *	compatible = "zephyr,power-state";
+ *	power-state-name = "suspend-to-idle";
+ *	substate-id = <1>;
+ *	min-residency-us = <200100>;
+ *	};
+ *	};
+ */
+};
+