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| author | David Huang <david.huang@quanta.corp-partner.google.com> | 2019-12-12 17:02:45 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-01-10 05:29:22 +0000 |
| commit | b5888e92487d846227ec048ea625ab0d099ff4fb (patch) | |
| tree | 7daa5267a43a0b5c15e63f3185ae5f71655f0136 | |
| parent | deaa645651c493ee3e46192dfeee09672f35e887 (diff) | |
| download | chrome-ec-b5888e92487d846227ec048ea625ab0d099ff4fb.tar.gz | |
Kindred: Add workaround for TI TPS51486RJER when system resume
Monitor GPIO PG_EC_ALL_SYS_PWRG was not trigger,
when power on within 3 seond, EC will reset system.
BUG=b:143440730
BRANCH=master
TEST=check boot to OS was workable
Change-Id: I19f2411a5369c75b6895316b791d077e2aee7deb
Signed-off-by: David Huang <David.Huang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1948690
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: David Huang <david.huang@quanta.corp-partner.google.com>
| -rw-r--r-- | board/kindred/board.c | 23 | ||||
| -rw-r--r-- | power/cometlake.c | 11 | ||||
| -rw-r--r-- | power/cometlake.h | 2 |
3 files changed, 36 insertions, 0 deletions
diff --git a/board/kindred/board.c b/board/kindred/board.c index 6ba4c949ea..99fbc47943 100644 --- a/board/kindred/board.c +++ b/board/kindred/board.c @@ -47,6 +47,10 @@ #define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) #define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +static void check_reboot_deferred(void); +DECLARE_DEFERRED(check_reboot_deferred); +static int system_in_resume_state = 0; + /* GPIO to enable/disable the USB Type-A port. */ const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = { GPIO_EN_USB_A_5V, @@ -477,3 +481,22 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0) else return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB)); } + +void all_sys_pgood_check_reboot(void) +{ + system_in_resume_state = 1; + hook_call_deferred(&check_reboot_deferred_data, 3000 * MSEC); +} + +static void all_sys_pgood_reset_reboot(void) +{ + system_in_resume_state = 0; +} +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, all_sys_pgood_reset_reboot, HOOK_PRIO_DEFAULT); + +static void check_reboot_deferred(void) +{ + if (!gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD) && system_in_resume_state == 1) { + system_reset(SYSTEM_RESET_MANUALLY_TRIGGERED); + } +} diff --git a/power/cometlake.c b/power/cometlake.c index 4a28cd418d..af30e750f1 100644 --- a/power/cometlake.c +++ b/power/cometlake.c @@ -111,6 +111,12 @@ enum power_state chipset_force_g3(void) return POWER_G3; } +/* Default no action, overwrite it in board.c if necessary*/ +__attribute__((weak)) void all_sys_pgood_check_reboot(void) +{ + return; +} + /* Called by APL power state machine when transitioning from G3 to S5 */ void chipset_pre_init_callback(void) { @@ -129,6 +135,11 @@ void chipset_pre_init_callback(void) * power_wait_signals() as PP5000_A_PGOOD is included in the * CHIPSET_G3S5_POWERUP_SIGNAL macro. */ + + /* For b:143440730, system might hang-up before enter S0/S3. Check + * GPIO_ALL_SYS_PGOOD here to make sure it will trigger every time. + */ + all_sys_pgood_check_reboot(); } enum power_state power_handle_state(enum power_state state) diff --git a/power/cometlake.h b/power/cometlake.h index 261e747eeb..6ef1277889 100644 --- a/power/cometlake.h +++ b/power/cometlake.h @@ -39,4 +39,6 @@ enum power_signal { POWER_SIGNAL_COUNT }; +void all_sys_pgood_check_reboot(void); + #endif /* __CROS_EC_COMETLAKE_H */ |