diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2018-02-07 19:37:52 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-02-08 12:58:20 -0800 |
| commit | d54cdec85b61f27f13bb6c089b5bd3fd05f014f2 (patch) | |
| tree | dbecc0288720180c91b1a6efa4f35e31dca8b112 | |
| parent | bbb707727d8586109b9cc9235a234de177652b1f (diff) | |
| download | chrome-ec-d54cdec85b61f27f13bb6c089b5bd3fd05f014f2.tar.gz | |
Fizz: Execute PMIC reset before vboot_main
When AP requests cold reboot, currently EC does not perform PMIC
reset because chipset_handle_reboot is executed only after EC jumps
to RW. This causes EC to miss CHIPSET_STARTUP and CHIPSET_RESUME
events because power rails do not cycle.
This patch will make EC execute PMIC reset to before vboot_main.
BUG=b:73093795
BRANCH=none
TEST=reboot, reboot ap-off, verify USB ports are powered after
transitionining to dev mode.
Change-Id: Ic04395d8a4bff45d9fc60601b07c600dfb75d9c0
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/908094
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
| -rw-r--r-- | common/main.c | 6 | ||||
| -rw-r--r-- | include/chipset.h | 5 | ||||
| -rw-r--r-- | power/skylake.c | 4 |
3 files changed, 14 insertions, 1 deletions
diff --git a/common/main.c b/common/main.c index 90d4a640c3..58f01812ef 100644 --- a/common/main.c +++ b/common/main.c @@ -7,6 +7,7 @@ #include "board_config.h" #include "button.h" +#include "chipset.h" #include "clock.h" #include "common.h" #include "console.h" @@ -171,6 +172,11 @@ test_mockable __keep int main(void) #if defined(CONFIG_VBOOT_EFS) /* + * Execute PMIC reset in case we're here after watchdog reset to unwedge + * AP. This has to be done here because vboot_main may jump to RW. + */ + chipset_handle_reboot(); + /* * For RO, it behaves as follows: * In recovery, it enables PD communication and returns. * In normal boot, it verifies and jumps to RW. diff --git a/include/chipset.h b/include/chipset.h index 5ada8c5c4b..c48eb733b8 100644 --- a/include/chipset.h +++ b/include/chipset.h @@ -104,6 +104,7 @@ static inline void chipset_force_shutdown(void) { } static inline void chipset_reset(int cold_reset) { } static inline void power_interrupt(enum gpio_signal signal) { } static inline void chipset_handle_espi_reset_assert(void) { } +static inline void chipset_handle_reboot(void) { } #endif /* !HAS_TASK_CHIPSET */ @@ -114,4 +115,8 @@ static inline void chipset_handle_espi_reset_assert(void) { } */ int chipset_pltrst_is_valid(void) __attribute__((weak)); +/** + * Execute chipset-specific reboot. + */ +void chipset_handle_reboot(void); #endif /* __CROS_EC_CHIPSET_H */ diff --git a/power/skylake.c b/power/skylake.c index 9cad5baaf4..61c07fb70e 100644 --- a/power/skylake.c +++ b/power/skylake.c @@ -124,7 +124,7 @@ __attribute__((weak)) int board_has_working_reset_flags(void) } #ifdef CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET -static void chipset_handle_reboot(void) +void chipset_handle_reboot(void) { int flags; @@ -167,5 +167,7 @@ static void chipset_handle_reboot(void) while (1) ; /* wait here */ } +#ifndef CONFIG_VBOOT_EFS DECLARE_HOOK(HOOK_INIT, chipset_handle_reboot, HOOK_PRIO_FIRST); #endif +#endif /* CONFIG_CHIPSET_HAS_PLATFORM_RESET */ |