hatch/kohaku: Account for TCPC reset polarity in ALERT handler

Reset polarity was added to tcpc_config so that the reset function
could be common across different boards which have different TCPC
selections. This was applied to pd_reset_mcu(), however, that CL did
not take into account the reset polarity in the tcpc_get_alert_status
function. This CL fixes that oversight.

In addition, this CL fixes the name for kohaku's port 0 TCPC reset
line to match the schematic.

BUG=b:130194031
BRANCH=none
TEST=verified on Hatch that both ports 0/1 function correctly.

Change-Id: I0d75d3655c799d4c74f4a6fb1805c06c1fe99c06
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1582964
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>

4 files changed, 13 insertions, 6 deletions

diff --git a/baseboard/hatch/baseboard.c b/baseboard/hatch/baseboard.c
index debdd015c3..2e9c23aa19 100644
--- a/baseboard/hatch/baseboard.c
+++ b/baseboard/hatch/baseboard.c
@@ -177,19 +177,23 @@ DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 uint16_t tcpc_get_alert_status(void)
 {
 	uint16_t status = 0;
+	int level;
 
 	/*
 	 * Check which port has the ALERT line set and ignore if that TCPC has
-	 * its reset line active. Note that port 0 reset is active high and
-	 * port 1 reset is active low.
+	 * its reset line active.
 	 */
 	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
-		if (!gpio_get_level(GPIO_USB_C0_TCPC_RST))
+		level = !!(tcpc_config[USB_PD_PORT_TCPC_0].flags &
+			   TCPC_FLAGS_RESET_ACTIVE_HIGH);
+		if (gpio_get_level(GPIO_USB_C0_TCPC_RST) != level)
 			status |= PD_STATUS_TCPC_ALERT_0;
 	}
 
 	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_TCPC_RST_ODL))
+		level = !!(tcpc_config[USB_PD_PORT_TCPC_1].flags &
+			   TCPC_FLAGS_RESET_ACTIVE_HIGH);
+		if (gpio_get_level(GPIO_USB_C1_TCPC_RST) != level)
 			status |= PD_STATUS_TCPC_ALERT_1;
 	}
 
@@ -225,7 +229,7 @@ void board_reset_pd_mcu(void)
 		      BOARD_TCPC_C0_RESET_POST_DELAY);
 
 	/* Reset TCPC1 */
-	reset_pd_port(USB_PD_PORT_TCPC_1, GPIO_USB_C1_TCPC_RST_ODL,
+	reset_pd_port(USB_PD_PORT_TCPC_1, GPIO_USB_C1_TCPC_RST,
 		      BOARD_TCPC_C1_RESET_HOLD_DELAY,
 		      BOARD_TCPC_C1_RESET_POST_DELAY);
 }
diff --git a/board/hatch/board.h b/board/hatch/board.h
index 869372096d..560b16d84b 100644
--- a/board/hatch/board.h
+++ b/board/hatch/board.h
@@ -56,6 +56,7 @@
 #define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
 #define BOARD_TCPC_C1_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
 #define BOARD_TCPC_C1_RESET_POST_DELAY 0
+#define GPIO_USB_C1_TCPC_RST GPIO_USB_C1_TCPC_RST_ODL
 
 /* USB Type A Features */
 #define CONFIG_USB_PORT_POWER_SMART
diff --git a/board/kohaku/board.h b/board/kohaku/board.h
index 7ef5f208de..558293f7a3 100644
--- a/board/kohaku/board.h
+++ b/board/kohaku/board.h
@@ -72,6 +72,8 @@
 #define BOARD_TCPC_C0_RESET_POST_DELAY 0
 #define BOARD_TCPC_C1_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
 #define BOARD_TCPC_C1_RESET_POST_DELAY 0
+#define GPIO_USB_C0_TCPC_RST GPIO_USB_C0_TCPC_RST_ODL
+#define GPIO_USB_C1_TCPC_RST GPIO_USB_C1_TCPC_RST_ODL
 
 /* BC 1.2 */
 #define CONFIG_BC12_DETECT_MAX14637
diff --git a/board/kohaku/gpio.inc b/board/kohaku/gpio.inc
index c695faad93..9e0e06fa30 100644
--- a/board/kohaku/gpio.inc
+++ b/board/kohaku/gpio.inc
@@ -58,7 +58,7 @@ GPIO(EC_INT_L,                 PIN(7, 0), GPIO_OUT_HIGH)
 
 /* USB and USBC Signals */
 GPIO(USB_C_OC_ODL,             PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST,          PIN(9, 7), GPIO_OUT_LOW)
+GPIO(USB_C0_TCPC_RST_ODL,      PIN(9, 7), GPIO_ODR_HIGH)
 GPIO(USB_C1_TCPC_RST_ODL,      PIN(3, 2), GPIO_ODR_HIGH)
 GPIO(USB_C0_BC12_CHG_DET_L,    PIN(0, 6), GPIO_INPUT)
 GPIO(USB_C1_BC12_CHG_DET_L,    PIN(3, 5), GPIO_INPUT)