diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2022-02-21 10:51:36 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2022-02-22 05:22:40 +0000 |
| commit | 86295f979ec39b8b522e75bb507830a57bf17dcc (patch) | |
| tree | 241b01cf51ee4f86aab9cf10c5c03c57d69ac26b | |
| parent | 32f92401dad8e18e21996c5a71ffb4b721f45cd9 (diff) | |
| download | chrome-ec-86295f979ec39b8b522e75bb507830a57bf17dcc.tar.gz | |
zephyr: it8xxx2: use 768KB space from flash
This change was made to use more space from flash.
Because Nereid image is almost out of space
(On previous test, the configuration still able to pass
software sync)
BRANCH=none
BUG=b:220273249
TEST=Build Nereid with enable CONFIG_PLATFORM_EC_BATTERY_CUT_OFF.
Verified sysjump command on Krabby.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I15445caa9cbf974128b4413d430569e844ef059d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3476659
Tested-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Commit-Queue: Peter Marheine <pmarheine@chromium.org>
| -rw-r--r-- | zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 | 12 | ||||
| -rw-r--r-- | zephyr/include/cros/ite/it8xxx2.dtsi | 8 | ||||
| -rw-r--r-- | zephyr/shim/include/config_chip.h | 4 |
3 files changed, 12 insertions, 12 deletions
diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 index dab9e6b8b2..809b9a6401 100644 --- a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 +++ b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 @@ -20,20 +20,20 @@ config CROS_EC_DATA_RAM_SIZE config CROS_EC_RAM_SIZE default 0x0000e000 -# The 512KB flash space layout are as the below: -# - RO image starts at the beginning of flash. -# - RW image starts at the second half of flash. +# The 768KB flash space layout are as the below: +# - RO image starts at the first 384k of flash. +# - RW image starts at the second 384k of flash. config CROS_EC_RO_MEM_OFF default 0x0 config CROS_EC_RO_SIZE - default 0x40000 + default 0x60000 config CROS_EC_RW_MEM_OFF - default 0x40000 + default 0x60000 config CROS_EC_RW_SIZE - default 0x40000 + default 0x60000 config FLASH_LOAD_OFFSET default CROS_EC_RW_MEM_OFF if CROS_EC_RW diff --git a/zephyr/include/cros/ite/it8xxx2.dtsi b/zephyr/include/cros/ite/it8xxx2.dtsi index c4108ebc82..38224b9fd4 100644 --- a/zephyr/include/cros/ite/it8xxx2.dtsi +++ b/zephyr/include/cros/ite/it8xxx2.dtsi @@ -90,15 +90,15 @@ }; }; - /* it8xxx2 has 1MB of flash. currently, we use 512KB from flash. */ + /* it8xxx2 has 1MB of flash. currently, we use 768KB from flash. */ binman { wp-ro { offset = <0x0>; - size = <0x40000>; + size = <0x60000>; }; ec-rw { - offset = <0x40000>; - size = <0x40000>; + offset = <0x60000>; + size = <0x60000>; }; }; }; diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h index 4366229a61..70926344c8 100644 --- a/zephyr/shim/include/config_chip.h +++ b/zephyr/shim/include/config_chip.h @@ -537,10 +537,10 @@ #ifdef CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES /* * Flash size of IT81202 is 1MB. - * We use only half space of flash to save time of erasing RW image from flash. + * We use only 3/4 space of flash to save time of erasing RW image from flash. */ #ifdef CONFIG_SOC_IT8XXX2 -#define CONFIG_FLASH_SIZE_BYTES (CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES / 2) +#define CONFIG_FLASH_SIZE_BYTES (CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES * 3 / 4) #else #define CONFIG_FLASH_SIZE_BYTES CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES #endif |