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authorCaveh Jalali <caveh@chromium.org>2022-02-14 15:25:14 -0800
committerCommit Bot <commit-bot@chromium.org>2022-02-25 04:52:31 +0000
commitd89485037f0a1824982900911a2465093f933faa (patch)
treed8ef726a2597bc414f2b6301b4ec31824d6a581d
parent60314954ccb7f95eba0d6e0d505df09b257e88a8 (diff)
downloadchrome-ec-d89485037f0a1824982900911a2465093f933faa.tar.gz
ps8xxx: Remove P1 designator from some regs
This renames the PS8815_P1_REG_RESERVED_F4 and PS8815_P1_REG_RESERVED_D1 to indicate they are on page 3. The original P1 naming was wrong. By convention, P3 registers do not include P3 in their name as that is the primary TCPM page. BRANCH=none BUG=b:183127346 TEST=buildall passes Change-Id: Ia6a8bcfafe277e2a871182d518e0f401b0319013 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3462928 Reviewed-by: Boris Mittelberg <bmbm@google.com>
-rw-r--r--driver/tcpm/ps8xxx.c8
-rw-r--r--driver/tcpm/ps8xxx.h8
2 files changed, 8 insertions, 8 deletions
diff --git a/driver/tcpm/ps8xxx.c b/driver/tcpm/ps8xxx.c
index b19384f2a2..7a2d03f704 100644
--- a/driver/tcpm/ps8xxx.c
+++ b/driver/tcpm/ps8xxx.c
@@ -740,8 +740,8 @@ __maybe_unused static int ps8815_tcpc_fast_role_swap_enable(int port,
* TODO(b/183127346): Confirm register write order
*/
status = tcpc_update8(port,
- PS8815_P1_REG_RESERVED_F4,
- PS8815_P1_REG_RESERVED_F4_FRS_EN,
+ PS8815_REG_RESERVED_F4,
+ PS8815_REG_RESERVED_F4_FRS_EN,
enable ? MASK_SET : MASK_CLR);
if (status != EC_SUCCESS)
return status;
@@ -852,8 +852,8 @@ static int ps8xxx_tcpm_init(int port)
*/
if (tcpm_tcpc_has_frs_control(port)) {
status = tcpc_update8(port,
- PS8815_P1_REG_RESERVED_D1,
- PS8815_P1_REG_RESERVED_D1_FRS_EN,
+ PS8815_REG_RESERVED_D1,
+ PS8815_REG_RESERVED_D1_FRS_EN,
MASK_SET);
if (status != EC_SUCCESS)
return status;
diff --git a/driver/tcpm/ps8xxx.h b/driver/tcpm/ps8xxx.h
index f7d0cacbf0..eeddd22640 100644
--- a/driver/tcpm/ps8xxx.h
+++ b/driver/tcpm/ps8xxx.h
@@ -68,10 +68,10 @@
#define PS8815_REG_APTX_EQ_AT_5G 0x24
#define PS8815_REG_RX_EQ_AT_5G 0x26
-#define PS8815_P1_REG_RESERVED_D1 0xD1
-#define PS8815_P1_REG_RESERVED_D1_FRS_EN BIT(7)
-#define PS8815_P1_REG_RESERVED_F4 0xF4
-#define PS8815_P1_REG_RESERVED_F4_FRS_EN BIT(6)
+#define PS8815_REG_RESERVED_D1 0xD1
+#define PS8815_REG_RESERVED_D1_FRS_EN BIT(7)
+#define PS8815_REG_RESERVED_F4 0xF4
+#define PS8815_REG_RESERVED_F4_FRS_EN BIT(6)
/*
* Below register is defined from Parade PS8815 Register Table,