diff options
| author | Devin Lu <Devin.Lu@quantatw.com> | 2022-02-25 16:56:32 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2022-03-15 07:03:22 +0000 |
| commit | 6b4ce2a74b27ba0d40479f49d54e44fa53ec8f87 (patch) | |
| tree | 0bcfbe530d4eaf90700759ff9ff9a1502672f1b1 | |
| parent | 63fc4e9543826c43e4f9b325fe57858437140b97 (diff) | |
| download | chrome-ec-6b4ce2a74b27ba0d40479f49d54e44fa53ec8f87.tar.gz | |
anahera: Tune USBA retimer EQ
Tune USBA retimer EQ for USB A0, USB A1 port.
BUG=b:203837657
BRANCH=none
TEST=i2cxfer to read setting is correct.
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Change-Id: Ia81d8a2559a3a9ac6c6b220fbd4bb31a83482a4d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3490453
Reviewed-by: caveh jalali <caveh@chromium.org>
| -rw-r--r-- | board/anahera/usbc_config.c | 62 | ||||
| -rw-r--r-- | board/anahera/usbc_config.h | 5 |
2 files changed, 67 insertions, 0 deletions
diff --git a/board/anahera/usbc_config.c b/board/anahera/usbc_config.c index 9c90e0af5e..247cc50dd3 100644 --- a/board/anahera/usbc_config.c +++ b/board/anahera/usbc_config.c @@ -317,15 +317,77 @@ const struct usb_mux usba_ps8811[] = { }; BUILD_ASSERT(ARRAY_SIZE(usba_ps8811) == USBA_PORT_COUNT); +const static struct ps8811_reg_val equalizer_table[] = { + { + /* Set channel A EQ setting */ + .reg = PS8811_REG1_USB_AEQ_LEVEL, + .val = (PS8811_AEQ_I2C_LEVEL_UP_10P5DB << + PS8811_AEQ_I2C_LEVEL_UP_SHIFT) | + (PS8811_AEQ_PIN_LEVEL_UP_18DB << + PS8811_AEQ_PIN_LEVEL_UP_SHIFT), + }, + { + /* Set ADE pin setting */ + .reg = PS8811_REG1_USB_ADE_CONFIG, + .val = (PS8811_ADE_PIN_MID_LEVEL_3DB << + PS8811_ADE_PIN_MID_LEVEL_SHIFT) | + PS8811_AEQ_CONFIG_REG_ENABLE | + PS8811_AEQ_ADAPTIVE_REG_ENABLE, + }, + { + /* Set channel B EQ setting */ + .reg = PS8811_REG1_USB_BEQ_LEVEL, + .val = (PS8811_BEQ_I2C_LEVEL_UP_10P5DB << + PS8811_BEQ_I2C_LEVEL_UP_SHIFT) | + (PS8811_BEQ_PIN_LEVEL_UP_18DB << + PS8811_BEQ_PIN_LEVEL_UP_SHIFT), + }, + { + /* Set BDE pin setting */ + .reg = PS8811_REG1_USB_BDE_CONFIG, + .val = (PS8811_BDE_PIN_MID_LEVEL_3DB << + PS8811_BDE_PIN_MID_LEVEL_SHIFT) | + PS8811_BEQ_CONFIG_REG_ENABLE, + }, +}; + +#define NUM_EQ_ARRAY ARRAY_SIZE(equalizer_table) + static int usba_retimer_init(int port) { int rv; int val; + int i; const struct usb_mux *me = &usba_ps8811[port]; rv = ps8811_i2c_read(me, PS8811_REG_PAGE1, PS8811_REG1_USB_BEQ_LEVEL, &val); + switch (port) { + case USBA_PORT_A0: + /* Set channel A output swing */ + rv = ps8811_i2c_field_update( + me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_A_SWING, + PS8811_CHAN_A_SWING_MASK, + 0x2 << PS8811_CHAN_A_SWING_SHIFT); + break; + case USBA_PORT_A1: + if (ec_cfg_has_lte()) { + /* Set channel A output swing */ + rv = ps8811_i2c_field_update( + me, PS8811_REG_PAGE1, + PS8811_REG1_USB_CHAN_A_SWING, + PS8811_CHAN_A_SWING_MASK, + 0x2 << PS8811_CHAN_A_SWING_SHIFT); + + for (i = 0; i < NUM_EQ_ARRAY; i++) + rv |= ps8811_i2c_write(me, PS8811_REG_PAGE1, + equalizer_table[i].reg, + equalizer_table[i].val); + } + break; + } + return rv; } diff --git a/board/anahera/usbc_config.h b/board/anahera/usbc_config.h index a34964af3b..b42c0f59fe 100644 --- a/board/anahera/usbc_config.h +++ b/board/anahera/usbc_config.h @@ -24,4 +24,9 @@ enum usbc_port { USBC_PORT_COUNT }; +struct ps8811_reg_val { + uint8_t reg; + uint16_t val; +}; + #endif /* __CROS_EC_USBC_CONFIG_H */ |