npcx: adc: support faster ADC conversion speed

In the ADC keyboard scan application, it requires higher ADC sampling
time to meet the keyboard scan timing specification.
To meet the timing constraint, this CL increases the ADC clock frequency
from ~2 to 7.5 MHz.
This change can apply to npcx7 and later chips because the basic clock
(APB1) of the ADC module is at 15 MHz.
For npcx5, the ADC clock frequency keeps at ~2 MHz because the APB1
clock is at (15/4) MHz.

BUG=b:208773873
BRANCH=none
test=read 8 ADC channels in board npcx9_evb via console command "adc";
it spent ~0.92 milli-seconds to read 8 ADC channels;
test = "make buildall"

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Ife59f667b1aafc926b2ad05209e7cc6185b82f21
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3505688
Reviewed-by: Parth Malkan <parthmalkan@google.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>

1 files changed, 25 insertions, 8 deletions

diff --git a/chip/npcx/adc.c b/chip/npcx/adc.c
index c15f739f45..a31a0376dd 100644
--- a/chip/npcx/adc.c
+++ b/chip/npcx/adc.c
@@ -24,11 +24,28 @@
 
 /* Maximum time we allow for an ADC conversion */
 #define ADC_TIMEOUT_US            SECOND
+/*
+ * ADC basic clock is from APB1.
+ * In npcx5, APB1 clock frequency is (15 MHz / 4).
+ * Configure ADC clock divider and speed parameters to set the ADC clock to
+ * ~2 MHz.
+ * In npcx7 and later chips, APB1 clock frequency is 15 MHz.
+ * Configure ADC clock divider and speed parameters to set the ADC clock to
+ * 7.5 MHz.
+ */
+#if defined(CHIP_FAMILY_NPCX5)
 #define ADC_CLK                   2000000
-#define ADC_REGULAR_DLY           0x11
-#define ADC_REGULAR_ADCCNF2       0x8B07
-#define ADC_REGULAR_GENDLY        0x0100
-#define ADC_REGULAR_MEAST         0x0001
+#define ADC_DLY                   0x03
+#define ADC_ADCCNF2               0x8B07
+#define ADC_GENDLY                0x0100
+#define ADC_MEAST                 0x0001
+#else
+#define ADC_CLK                   7500000
+#define ADC_DLY                   0x02
+#define ADC_ADCCNF2               0x8901
+#define ADC_GENDLY                0x0100
+#define ADC_MEAST                 0x0405
+#endif
 
 /* ADC conversion mode */
 enum npcx_adc_conversion_mode {
@@ -419,12 +436,12 @@ void adc_init(void)
 	adc_freq_changed();
 
 	/* Set regular speed */
-	SET_FIELD(NPCX_ATCTL, NPCX_ATCTL_DLY_FIELD, (ADC_REGULAR_DLY - 1));
+	SET_FIELD(NPCX_ATCTL, NPCX_ATCTL_DLY_FIELD, ADC_DLY);
 
 	/* Set the other ADC settings */
-	NPCX_ADCCNF2 = ADC_REGULAR_ADCCNF2;
-	NPCX_GENDLY = ADC_REGULAR_GENDLY;
-	NPCX_MEAST = ADC_REGULAR_MEAST;
+	NPCX_ADCCNF2 = ADC_ADCCNF2;
+	NPCX_GENDLY = ADC_GENDLY;
+	NPCX_MEAST = ADC_MEAST;
 
 	task_waiting = TASK_ID_INVALID;