Zephyr: Add initial code to enable Meteorlake RVP

Added in support for the initial Meteorlake RVP code base. This patch enables
minimal features in order to get the system to enter S0.

BUG=none
BRANCH=none
TEST=zmake mtlrvpp_npcx and verify system enters s0 on EC console

Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Change-Id: I66ec23bbe1e3f22d07679565454b72b4de4a5152
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3516598
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Keith Short <keithshort@chromium.org>

14 files changed, 519 insertions, 0 deletions

diff --git a/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml b/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml
index d5d8c92525..620c3fe98c 100644
--- a/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml
+++ b/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml
@@ -42,6 +42,8 @@ properties:
     - I2C_PORT_TYPEC_1
     - I2C_PORT_TYPEC_2
     - I2C_PORT_TYPEC_3
+    - I2C_PORT_TYPEC_AIC_1
+    - I2C_PORT_TYPEC_AIC_2
     - I2C_PORT_USB_1_MIX
     - I2C_PORT_USB_C0
     - I2C_PORT_USB_C0_TCPC
diff --git a/zephyr/projects/intelrvp/BUILD.py b/zephyr/projects/intelrvp/BUILD.py
index 3c4a65c853..264848b005 100644
--- a/zephyr/projects/intelrvp/BUILD.py
+++ b/zephyr/projects/intelrvp/BUILD.py
@@ -21,6 +21,9 @@ def register_intelrvp_project(
         kconfig_files.append(here / "adlrvp/prj.conf")
         dts_overlays.append(here / "adlrvp/battery.dts")
         dts_overlays.append(here / "adlrvp/ioex.dts")
+    if project_name.startswith("mtlrvp"):
+        kconfig_files.append(here / "mtlrvp/prj.conf")
+        dts_overlays.append(here / "mtlrvp/battery.dts")
     kconfig_files.extend(extra_kconfig_files)
     dts_overlays.extend(extra_dts_overlays)
 
@@ -44,3 +47,15 @@ register_intelrvp_project(
     ],
     extra_kconfig_files=[here / "adlrvp/adlrvp_npcx/prj.conf"],
 )
+
+register_intelrvp_project(
+    project_name="mtlrvpp_npcx",
+    chip="npcx9",
+    extra_dts_overlays=[
+        here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts",
+        here / "mtlrvp/mtlrvpp_npcx/fan.dts",
+        here / "mtlrvp/mtlrvpp_npcx/gpio.dts",
+        here / "mtlrvp/mtlrvpp_npcx/interrupts.dts",
+    ],
+    extra_kconfig_files=[here / "mtlrvp/mtlrvpp_npcx/prj.conf"],
+)
diff --git a/zephyr/projects/intelrvp/CMakeLists.txt b/zephyr/projects/intelrvp/CMakeLists.txt
index 6585f3b159..5995dd8791 100644
--- a/zephyr/projects/intelrvp/CMakeLists.txt
+++ b/zephyr/projects/intelrvp/CMakeLists.txt
@@ -13,3 +13,8 @@ if(DEFINED CONFIG_BOARD_ADLRVP_NPCX)
   add_subdirectory(adlrvp)
   zephyr_library_sources("src/intelrvp.c")
 endif()
+
+if(DEFINED CONFIG_BOARD_MTLRVP_NPCX)
+  add_subdirectory(mtlrvp)
+  zephyr_library_sources("src/intelrvp.c")
+endif()
diff --git a/zephyr/projects/intelrvp/Kconfig b/zephyr/projects/intelrvp/Kconfig
index 0a1f40bfdd..4da2917448 100644
--- a/zephyr/projects/intelrvp/Kconfig
+++ b/zephyr/projects/intelrvp/Kconfig
@@ -9,4 +9,11 @@ config BOARD_ADLRVP_NPCX
 	  Build Intel ADLRVP_NPCX reference board. This board has Intel ADL RVP
 	  SoC with NPCX9M3F EC.
 
+config BOARD_MTLRVP_NPCX
+	bool "Intel MTLRVP_NPCX board"
+	depends on SOC_NPCX9M3F
+	help
+	  Build Intel MTLRVP_NPCX reference board. This board is Intel MTL RVP
+	  SOC with NPCX_NPCX9M3F
+
 source "Kconfig.zephyr"
diff --git a/zephyr/projects/intelrvp/include/gpio_map.h b/zephyr/projects/intelrvp/include/gpio_map.h
index 683f8d1fff..5e28524b52 100644
--- a/zephyr/projects/intelrvp/include/gpio_map.h
+++ b/zephyr/projects/intelrvp/include/gpio_map.h
@@ -8,4 +8,9 @@
 
 #define GPIO_EN_PP5000                  GPIO_UNIMPLEMENTED
 
+/* TODO: Implement GPIO_ENTERING_RW in IOEX */
+#ifdef CONFIG_BOARD_MTLRVP_NPCX
+#define GPIO_ENTERING_RW		GPIO_UNIMPLEMENTED
+#endif /* CONFIG_BOARD_MTLRVP_NPCK */
+
 #endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt b/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt
new file mode 100644
index 0000000000..75015a1068
--- /dev/null
+++ b/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources("src/mtlrvp.c")
diff --git a/zephyr/projects/intelrvp/mtlrvp/battery.dts b/zephyr/projects/intelrvp/mtlrvp/battery.dts
new file mode 100644
index 0000000000..5287064adc
--- /dev/null
+++ b/zephyr/projects/intelrvp/mtlrvp/battery.dts
@@ -0,0 +1,15 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	batteries {
+		default_battery: getac_smp_hhp_408_3s {
+			compatible = "getac,bq40z50-R3-S3";
+		};
+		getac_smp_hhp_408_2s {
+			compatible = "getac,bq40z50-R3-S2";
+		};
+	};
+};
diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts
new file mode 100644
index 0000000000..3253f38691
--- /dev/null
+++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts
@@ -0,0 +1,35 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+        named-fans {
+                compatible = "named-fans";
+
+                fan_0 {
+                        label = "FAN_0";
+                        pwms = <&pwm3 0 PWM_POLARITY_NORMAL>;
+                        pwm-frequency = <30000>;
+                        rpm_min = <2200>;
+                        rpm_start = <2200>;
+                        rpm_max = <4200>;
+                        tach = <&tach2>;
+                };
+        };
+};
+
+/* Tachemeter for fan speed measurement */
+&tach2 {
+        status = "okay";
+        pinctrl-0 = <&altc_ta2_sl2>; /* Use TA2 as input pin */
+        port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+        sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+        pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&pwm3 {
+        status = "okay";
+        drive-open-drain;
+};
+
diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts
new file mode 100644
index 0000000000..fc2a7448c3
--- /dev/null
+++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts
@@ -0,0 +1,276 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_wp;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		ioex_kbd_intr_n: ioex-kbd-intr-n {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+		};
+		all_sys_pwrgd: all-sys-pwrgd {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+			enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD";
+		};
+		rsmrst_pwrgd: rsmrst-pwrgd {
+			gpios = <&gpio6 6 GPIO_INPUT>; /* 1.8V */
+			enum-name = "GPIO_PG_EC_RSMRST_ODL";
+		};
+		pch_slp_s0_n: pch-slp-s0-n-ec {
+			gpios = <&gpioa 1 GPIO_INPUT>;
+			enum-name = "GPIO_PCH_SLP_S0_L"; /* 1.8V */
+		};
+		pm-slp-s3-n-ec {
+			gpios = <&gpiob 0 GPIO_INPUT>; /* 1.8V */
+		};
+		pm-slp-s4-n-ec {
+			gpios = <&gpioa 5 GPIO_INPUT>; /* 1.8V */
+		};
+		volume-up {
+			gpios = <&gpio6 1 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		vol-dn-ec-r {
+			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		smc_lid: smc-lid {
+			gpios = <&gpio0 1 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		smc_onoff_n: smc-onoff-n {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_wp: wp-l {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+		};
+		std-adp-prsnt {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+		};
+		bc_acok: bc-acok-ec {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		usbc-tcpc-alrt-p0 {
+			gpios = <&gpio4 0 GPIO_INPUT>;
+		};
+		/* NOTE: Netname is USBC_TCPC_PPC_ALRT_P0 */
+		usb-c0-c1-tcpc-rst-odl {
+			gpios = <&gpiod 0 GPIO_ODR_HIGH>;
+		};
+		/* NOTE: Netname is USBC_TCPC_ALRT_P1 */
+		usbc-tcpc-ppc-alrt-p0 {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+		};
+		usbc-tcpc-ppc-alrt-p1 {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+		};
+		usbc-tcpc-alrt-p2 {
+			gpios = <&gpio9 1 GPIO_INPUT>;
+		};
+		/* NOTE: Netname is USBC_TCPC_PPC_ALRT_P3 */
+		usbc-tcpc-ppc-alrt-p3 {
+			gpios = <&gpiof 3 GPIO_INPUT>;
+		};
+		gpio_ec_pch_wake_odl: pch-wake-n {
+			gpios = <&gpio7 4 GPIO_ODR_HIGH>;
+		};
+		espi-rst-n {
+			gpios = <&gpio5 4 GPIO_INPUT>; /* 1.8V */
+		};
+		plt-rst-l {
+			gpios = <&gpioa 2 GPIO_INPUT>; /* 1.8V */
+		};
+		slate-mode-indication {
+			gpios = <&gpio9 4 GPIO_INPUT>; /* 1.8V */
+		};
+		prochot-ec {
+			gpios = <&gpio6 0 GPIO_INPUT>;
+			enum-name = "GPIO_CPU_PROCHOT";
+		};
+		sys-rst-odl-ec {
+			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_SYS_RESET_L";
+		};
+		pm-rsmrst-r-n {
+			gpios = <&gpioa 4 GPIO_OUTPUT_LOW>; /* 1.8V */
+			enum-name = "GPIO_PCH_RSMRST_L";
+		};
+		pm-pwrbtn-n-ec {
+			gpios = <&gpiod 4 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		ec_spi_oe_mecc: ec-spi-oe-mecc-r {
+			gpios = <&gpioa 7 GPIO_OUTPUT_LOW>; /* 1.8V */
+		};
+		ec-ds3-r {
+			gpios = <&gpioc 4 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_PP3300_A";
+		};
+		pch-pwrok-ec-r {
+			gpios = <&gpiod 3 GPIO_INPUT>;
+		};
+		sys_pwrok_ec: sys-pwrok-ec {
+			gpios = <&gpiof 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PCH_SYS_PWROK";
+		};
+		bat-det-ec {
+			gpios = <&gpio7 6 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		edp-bklt-en {
+			gpios = <&gpioe 1 GPIO_OUTPUT_HIGH>;
+		};
+		/* TODO: move both LEDs to PWM */
+		led-1-l-ec {
+			gpios = <&gpiob 6 GPIO_OUTPUT_HIGH>;
+		};
+		led-2-l-ec {
+			gpios = <&gpiob 7 GPIO_OUTPUT_HIGH>;
+		};
+		therm-sen-mecc-r {
+			gpios = <&gpioc 0 GPIO_OUTPUT_LOW>;
+		};
+		/* NOTE: Netname is USBC_TCPC_ALRT_P3 */
+		ccd-mode-odl {
+			gpios = <&gpio9 2 GPIO_INPUT>;
+		};
+		smb-bs-clk {
+			gpios = <&gpiob 3 GPIO_INPUT>;
+		};
+		smb-bs-data {
+			gpios = <&gpiob 2 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-clk-aic1 {
+			gpios = <&gpiob 5 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-data-aic1 {
+			gpios = <&gpiob 4 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-clk-aic2 {
+			gpios = <&gpio9 0 GPIO_INPUT>;
+		};
+		usbc-tcpc-i2c-data-aic2 {
+			gpios = <&gpio8 7 GPIO_INPUT>;
+		};
+		/* Unused 1.8V pins */
+		i3c-1-sda-r {
+			gpios = <&gpio5 0 GPIO_INPUT>;
+		};
+		i3c-1-scl-r {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+		};
+		espi-alert0-n-r {
+			gpios = <&gpio5 7 GPIO_INPUT>;
+		};
+		tp-gpio95 {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+		};
+		cpu-c10-gate {
+			gpios = <&gpio9 6 GPIO_INPUT>;
+		};
+		slp-s0-cs-n-ec {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+		};
+		rtc-rst-n-r {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+		};
+		tp-gpioa6 {
+			gpios = <&gpioa 6 GPIO_INPUT>;
+		};
+		sml1-clk-mecc {
+			gpios = <&gpio3 3 GPIO_INPUT>;
+		};
+		sml1-data-mecc {
+			gpios = <&gpio3 6 GPIO_INPUT>;
+		};
+		sml1-alert {
+			gpios = <&gpioc 7 GPIO_INPUT>;
+		};
+		smb-pch-alrt {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+		};
+		smb-pch-data {
+			gpios = <&gpioc 1 GPIO_INPUT>;
+		};
+		smb-pch-clk {
+			gpios = <&gpioc 2 GPIO_INPUT>;
+		};
+		/* Unused 3.3V pins */
+		cpu-cat-err-mecc {
+			gpios = <&gpio3 4 GPIO_INPUT>;
+		};
+		tp-gpio37 {
+			gpios = <&gpio3 7 GPIO_INPUT>;
+		};
+		tp-vccpdsw-3p3-ec {
+			gpios = <&gpio4 5 GPIO_INPUT>;
+		};
+		mech-pwr-btn-in-odl {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+		};
+		tp-gpio63 {
+			gpios = <&gpio6 3 GPIO_INPUT>;
+		};
+		tp-gpio67 {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		tp-gpio72 {
+			gpios = <&gpio7 2 GPIO_INPUT>;
+		};
+		tp-gpio75 {
+			gpios = <&gpio7 5 GPIO_INPUT>;
+		};
+		ec-peci-ec {
+			gpios = <&gpio8 1 GPIO_INPUT>;
+		};
+		tp-gpiob1 {
+			gpios = <&gpiob 1 GPIO_INPUT>;
+		};
+		std-adpt-cntrl-GPIO_r {
+			gpios = <&gpioc 3 GPIO_INPUT>;
+		};
+		ec-packet-mode-ec {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+		};
+		tp-gpioe3 {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+		};
+		boot-stall-r {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+		};
+		tp-gpiof0 {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		tp-gpiof1 {
+			gpios = <&gpiof 1 GPIO_INPUT>;
+		};
+		usbc-tcpc-ppc-alrt-p2 {
+			gpios = <&gpiof 2 GPIO_INPUT>;
+		};
+		tp-gpiof4 {
+			gpios = <&gpiof 4 GPIO_INPUT>;
+		};
+	};
+
+	def-lvol-io-list {
+		compatible = "nuvoton,npcx-lvolctrl-def";
+		lvol-io-pads = <
+			&lvol_io66 /* RSMRET_PWRGD */
+			&lvol_io90 /* I2C1_SCL0 */
+			&lvol_io87 /* I2C1_SDA0 */
+			&lvol_io33 /* SML1_CLK_MECC */
+			&lvol_io36 /* SML1_DATA_MECC */
+			&lvol_ioc7 /* SML1_ALERT */
+			&lvol_ioc1 /* SMB_PCH_DATA */
+			&lvol_ioc2 /* SMB_PCH_CLK */
+		>;
+	};
+};
diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts
new file mode 100644
index 0000000000..e9e5587343
--- /dev/null
+++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts
@@ -0,0 +1,40 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_lid_open: lid_open {
+			irq-pin = <&smc_lid>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_power_button: power_button {
+			irq-pin = <&smc_onoff_n>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_ac_present: ac_present {
+			irq-pin = <&bc_acok>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_slp_s0: slp_s0 {
+			irq-pin = <&pch_slp_s0_n>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_rsmrst_pwrgd: rsmrst_pwrgd {
+			irq-pin = <&rsmrst_pwrgd>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_all_sys_pwrgd: all_sys_pwrgd {
+			irq-pin = <&all_sys_pwrgd>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+	};
+};
diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts
new file mode 100644
index 0000000000..3076e239ac
--- /dev/null
+++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts
@@ -0,0 +1,57 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		battery {
+			i2c-port = <&i2c7_0>;
+			enum-name = "I2C_PORT_BATTERY";
+		};
+		charger {
+			i2c-port = <&i2c7_0>;
+			enum-name = "I2C_PORT_CHARGER";
+		};
+		typec_aic1 {
+			i2c-port = <&i2c0_0>;
+			enum-name = "I2C_PORT_TYPEC_AIC_1";
+		};
+		typec_aic2 {
+			i2c-port = <&i2c2_0>;
+			enum-name = "I2C_PORT_TYPEC_AIC_2";
+		};
+	};
+};
+
+/* charger */
+&i2c7_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
+
+/* typec_aic1 */
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+/* typec_aic2 */
+&i2c2_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf
new file mode 100644
index 0000000000..fa1c0cb305
--- /dev/null
+++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf
@@ -0,0 +1,12 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_MTLRVP_NPCX=y
+CONFIG_CROS_FLASH_NPCX=y
+CONFIG_CROS_SYSTEM_NPCX=y
+CONFIG_SYSCON=y
+
+# PWM
+CONFIG_PWM=y
+CONFIG_PWM_SHELL=n
diff --git a/zephyr/projects/intelrvp/mtlrvp/prj.conf b/zephyr/projects/intelrvp/mtlrvp/prj.conf
new file mode 100644
index 0000000000..b0c83e2d9f
--- /dev/null
+++ b/zephyr/projects/intelrvp/mtlrvp/prj.conf
@@ -0,0 +1,17 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Power Sequencing
+CONFIG_AP_X86_INTEL_MTL=y
+CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE=n
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+CONFIG_PLATFORM_EC_POWERSEQ_METEORLAKE=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT=y
+
+# TODO: Enable these in follow on CLs
+CONFIG_PLATFORM_EC_KEYBOARD=n
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
+CONFIG_PLATFORM_EC_VBOOT_EFS2=n
diff --git a/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c b/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c
new file mode 100644
index 0000000000..3f6762d6be
--- /dev/null
+++ b/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c
@@ -0,0 +1,28 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "gpio.h"
+#include "power/meteorlake.h"
+
+/******************************************************************************/
+/* PWROK signal configuration */
+/*
+ * On MTLRVP, SYS_PWROK_EC is an output controlled by EC and uses ALL_SYS_PWRGD
+ * as input.
+ */
+const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
+	{
+		.gpio = GPIO_PCH_SYS_PWROK,
+		.delay_ms = 3,
+	},
+};
+const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
+	{
+		.gpio = GPIO_PCH_SYS_PWROK,
+	},
+};
+const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list);