diff options
| author | Peter Marheine <pmarheine@chromium.org> | 2022-03-25 00:14:24 +0000 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-03-25 08:22:35 +0000 |
| commit | da3901660fad87875f4931983c8ee94cd40bbb5d (patch) | |
| tree | b48dead5f9180f6c71e252ae03745f85530da6fc | |
| parent | 01ad8cb9cfcf3ca1d99d3436ced6518742251a0c (diff) | |
| download | chrome-ec-da3901660fad87875f4931983c8ee94cd40bbb5d.tar.gz | |
ap_pwrseq: emit a PRE_INIT event on G3->S5 transition
There is currently no event that gets emitted for the G3->S5 transition,
but legacy ARM boards use PRE_INIT in a similar way. Legacy ARM power code
emits PRE_INIT on transition from S5 to S3, but that is the transition
in which SoC power is first applied because they lack a soft-off state
similar to S5.
Since this adds new meaning to PRE_INIT where it was previously unclear,
the event is documented to be the transition from G3 to S5.
BUG=b:226215993,b:226513200
TEST=PRE_INIT is now emitted on S5 entry on Nereid
BRANCH=none
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I3ca64a309221c87583d8ae5ea8806f5ee465b0df
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3551996
Reviewed-by: Andrew McRae <amcrae@google.com>
Reviewed-by: Li1 Feng <li1.feng@intel.com>
| -rw-r--r-- | zephyr/include/ap_power/ap_power.h | 5 | ||||
| -rw-r--r-- | zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c | 4 |
2 files changed, 8 insertions, 1 deletions
diff --git a/zephyr/include/ap_power/ap_power.h b/zephyr/include/ap_power/ap_power.h index 4aceef8bcd..0a073f1a71 100644 --- a/zephyr/include/ap_power/ap_power.h +++ b/zephyr/include/ap_power/ap_power.h @@ -21,6 +21,11 @@ * @brief AP power events for callback notification. */ enum ap_power_events { + /** + * Transitioning from hard-off to soft-off. + * + * On x86 this is the transition up from G3 to S5. + */ AP_POWER_PRE_INIT = BIT(0), AP_POWER_STARTUP = BIT(1), AP_POWER_RESUME = BIT(2), diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c index 33b14c1cec..3d861135ef 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c @@ -183,8 +183,10 @@ static int common_pwr_sm_run(int state) * Now wait for SLP_SUS_L to go high based on tPCH32. If this * signal doesn't go high within 250 msec then go back to G3. */ - if (check_pch_out_of_suspend()) + if (check_pch_out_of_suspend()) { + ap_power_ev_send_callbacks(AP_POWER_PRE_INIT); return SYS_POWER_STATE_S5; + } return SYS_POWER_STATE_S5G3; case SYS_POWER_STATE_S5: |