snoball: Add support for proto 0.9 board

This board uses a different stm32f0 MCU and has significant
architectural changes.

BUG=chrome-os-partner:50549
BRANCH=None
TEST=`make buildall -j`, verify snoball boots to console

Change-Id: I842a3efc5e179b33bbf0441e8d4ea07fa006e3fe
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/329439
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>

7 files changed, 91 insertions, 163 deletions

diff --git a/board/snoball/board.c b/board/snoball/board.c
index 7efa5b314b..ee545d736a 100644
--- a/board/snoball/board.c
+++ b/board/snoball/board.c
@@ -9,91 +9,55 @@
 #include "adc_chip.h"
 #include "common.h"
 #include "console.h"
-#include "fusb302.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "i2c.h"
 #include "registers.h"
-#include "pwm.h"
-#include "pwm_chip.h"
 #include "task.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
 #include "util.h"
 
 void tcpc_alert_event(enum gpio_signal signal)
 {
 	/* Exchange status with TCPCs */
-	host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
+	ccprintf("TCPC alert!\n");
 }
 
 #include "gpio_list.h"
 
 const struct i2c_port_t i2c_ports[] = {
-	{"tcpc-a", STM32_I2C1_PORT, 1000, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc-b", STM32_I2C2_PORT, 1000, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{"tcpc-a", STM32_I2C1_PORT, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
+	{"tcpc-b", STM32_I2C2_PORT, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_COUNT] = {
-	{STM32_I2C1_PORT, FUSB302_I2C_SLAVE_ADDR, &fusb302_tcpm_drv},
-	{STM32_I2C2_PORT, FUSB302_I2C_SLAVE_ADDR, &fusb302_tcpm_drv},
-	/* TODO: Verify secondary slave addr, or use i2c mux */
-	{STM32_I2C2_PORT, FUSB302_I2C_SLAVE_ADDR + 2, &fusb302_tcpm_drv},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_TCPC1_INT))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_TCPC2_INT))
-		status |= PD_STATUS_TCPC_ALERT_1;
-	if (!gpio_get_level(GPIO_TCPC3_INT))
-		status |= PD_STATUS_TCPC_ALERT_2;
-
-	return status;
-}
-
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	/* Current sensing. Converted to mA (6600mV/4096). */
-	[ADC_C0_CS] = {"C0_CS", 6600, 4096, 0, STM32_AIN(0)},
-	[ADC_C1_CS] = {"C1_CS", 6600, 4096, 0, STM32_AIN(1)},
-	[ADC_C2_CS] = {"C2_CS", 6600, 4096, 0, STM32_AIN(2)},
-	/* Voltage sensing. Converted to mV (40000mV/4096). */
-	[ADC_C0_VS] = {"C0_VS", 40000, 4096, 0, STM32_AIN(3)},
-	[ADC_C1_VS] = {"C1_VS", 40000, 4096, 0, STM32_AIN(4)},
-	[ADC_C2_VS] = {"C2_VS", 40000, 4096, 0, STM32_AIN(5)},
-	[ADC_VBUCK] = {"VBUCK",  40000, 4096, 0, STM32_AIN(8)},
-	/* TODO: Check characteristics of thermistor circuit */
-	[ADC_TEMP] = {"TEMP", 3300, 4096, 0, STM32_AIN(9)},
+	/* VBIAS input voltage, through /2 divider. */
+	[ADC_VBIAS] = {"VBIAS", 6600, 4096, 0, STM32_AIN(4)},
+	[ADC_VOUT_1] = {"VOUT_1", 39600, 4096, 0, STM32_AIN(5)},
+	[ADC_VOUT_2] = {"VOUT_2", 39600, 4096, 0, STM32_AIN(6)},
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-#define VR_PWM_FLAGS (PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_COMPLEMENTARY_OUTPUT)
-
-const struct pwm_t pwm_channels[] = {
-	{STM32_TIM(15), STM32_TIM_CH(1), VR_PWM_FLAGS, 480000},
-	{STM32_TIM(16), STM32_TIM_CH(1), VR_PWM_FLAGS, 480000},
-	{STM32_TIM(17), STM32_TIM_CH(1), VR_PWM_FLAGS, 480000},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 static void board_init(void)
 {
 	gpio_enable_interrupt(GPIO_TCPC1_INT);
 	gpio_enable_interrupt(GPIO_TCPC2_INT);
-	gpio_enable_interrupt(GPIO_TCPC3_INT);
-
-	pwm_enable(PWM_PD1, 1);
-	pwm_enable(PWM_PD2, 1);
-	pwm_enable(PWM_PD3, 1);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-void board_reset_pd_mcu(void)
+void board_config_pre_init(void)
 {
+	/* enable SYSCFG clock */
+	STM32_RCC_APB2ENR |= 1 << 0;
+	/*
+	 * the DMA mapping is :
+	 *  Chan 4 : USART1_TX
+	 *  Chan 5 : USART1_RX
+	 */
+
+	/* Remap USART1 RX/TX DMA to match uart driver. */
+	STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);
 }
diff --git a/board/snoball/board.h b/board/snoball/board.h
index f7e27a5038..46fc41326d 100644
--- a/board/snoball/board.h
+++ b/board/snoball/board.h
@@ -8,39 +8,46 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
 /* the UART console is on USART1 (PA9/PA10) */
 #define CONFIG_UART_CONSOLE 1
-/* Use DMA channels 2 + 3 (rather than default 4 + 5) */
-#define CONFIG_UART_TX_DMA_CH STM32_DMAC_CH2
-#define CONFIG_UART_RX_DMA_CH STM32_DMAC_CH3
-
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_ALT_MODE
-/* TODO: Consider disabling PD communication in RO */
-#define CONFIG_USB_PD_CUSTOM_VDM
-#define CONFIG_USB_PD_DYNAMIC_SRC_CAP
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_LOG_SIZE 1024
-#define CONFIG_USB_PD_PORT_COUNT 3
-#define CONFIG_USB_PD_TCPM_FUSB302
+
+/*
+ * The console task is too big to include in both RO and RW images. Therefore,
+ * if the console task is defined, then only build an RW image. This can be
+ * useful for debugging to have a full console. Otherwise, without this task,
+ * a full RO and RW is built with a limited one-way output console.
+ */
+#ifdef HAS_TASK_CONSOLE
+#undef CONFIG_FW_INCLUDE_RO
+#undef CONFIG_RW_MEM_OFF
+#define CONFIG_RW_MEM_OFF 0
+#undef CONFIG_RO_SIZE
+#define CONFIG_RO_SIZE 0
+/* Fake full size if we had a RO partition */
+#undef CONFIG_RW_SIZE
+#define CONFIG_RW_SIZE CONFIG_FLASH_SIZE
+
+#else
+#define CONFIG_DEBUG_PRINTF
+#define UARTN CONFIG_UART_CONSOLE
+#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
+#endif
+
+/* 48 MHz SYSCLK clock frequency */
+#define CPU_CLOCK 48000000
 
 #define CONFIG_ADC
+#undef  CONFIG_ADC_WATCHDOG
+#define CONFIG_BOARD_PRE_INIT
 #define CONFIG_HW_CRC
 #define CONFIG_I2C
 #define CONFIG_I2C_MASTER
-#define CONFIG_PWM
 #undef CONFIG_LID_SWITCH
 #undef CONFIG_WATCHDOG_HELP
 
-/* USB configuration */
-#define CONFIG_USB_PID 0x5019
-#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
+#define CONFIG_LTO
 
 #define CONFIG_HIBERNATE
-#define CONFIG_HIBERNATE_WAKEUP_PINS STM32_PWR_CSR_EWUP6
 
 /*
  * Allow dangerous commands all the time, since we don't have a write protect
@@ -53,47 +60,18 @@
 /* Timer selection */
 #define TIM_CLOCK_MSB 3
 #define TIM_CLOCK_LSB 1
-#define TIM_ADC 14
 
 #include "gpio_signal.h"
 
 /* ADC signals */
 enum adc_channel {
-	ADC_C0_CS,
-	ADC_C1_CS,
-	ADC_C2_CS,
-	ADC_C0_VS,
-	ADC_C1_VS,
-	ADC_C2_VS,
-	ADC_VBUCK,
-	ADC_TEMP,
+	ADC_VBIAS,
+	ADC_VOUT_1,
+	ADC_VOUT_2,
 	/* Number of ADC channels */
 	ADC_CH_COUNT
 };
 
-enum pwm_channel {
-	PWM_PD1 = 0,
-	PWM_PD2,
-	PWM_PD3,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum board_src_cap {
-	SRC_CAP_5V = 0,
-	SRC_CAP_12V,
-	SRC_CAP_20V,
-};
-
-#define PD_DEFAULT_STATE PD_STATE_SRC_DISCONNECTED
-
-/* delay necessary for the voltage transition on the power supply */
-/* TODO: Tune these parameters appropriately for snoball */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
-
-void board_reset_pd_mcu(void);
-
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/snoball/build.mk b/board/snoball/build.mk
index 3864212b62..ce52e7678f 100644
--- a/board/snoball/build.mk
+++ b/board/snoball/build.mk
@@ -5,10 +5,13 @@
 #
 # Board specific files build
 
-# the IC is STmicro STM32F070CB
+# the IC is STmicro STM32F030C8
 CHIP:=stm32
 CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f070
+CHIP_VARIANT:=stm32f03x8
 
 board-y=board.o
 board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
+
+# This target builds RW only.  Therefore, remove RO from dependencies.
+all_deps=$(patsubst ro,,$(def_all_deps))
diff --git a/board/snoball/ec.tasklist b/board/snoball/ec.tasklist
index e9564d8f68..2aa156bdd3 100644
--- a/board/snoball/ec.tasklist
+++ b/board/snoball/ec.tasklist
@@ -18,8 +18,4 @@
  */
 #define CONFIG_TASK_LIST \
 	TASK_ALWAYS(HOOKS,   hook_task,       NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(PDCMD,   pd_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task,    NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0,   pd_task,         NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1,   pd_task,         NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C2,   pd_task,         NULL, LARGER_TASK_STACK_SIZE)
+	TASK_ALWAYS(CONSOLE, console_task,    NULL, TASK_STACK_SIZE)
diff --git a/board/snoball/gpio.inc b/board/snoball/gpio.inc
index d9c925a336..d92a999c6b 100644
--- a/board/snoball/gpio.inc
+++ b/board/snoball/gpio.inc
@@ -9,35 +9,30 @@
  * Note: Those with interrupt handlers must be declared first. */
 
 /* TCPC alert / interrupt inputs */
-GPIO_INT(TCPC1_INT,	PIN(A, 11),	GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(TCPC2_INT,	PIN(A, 12),	GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(TCPC3_INT,	PIN(A, 13),	GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(TCPC1_INT,	PIN(A, 0),	GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event)
+GPIO_INT(TCPC2_INT,	PIN(C, 13),	GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event)
 
 /* ADCs */
-GPIO(PD1_CURRENT_SENSE,	PIN(A, 0),	GPIO_ANALOG)
-GPIO(PD2_CURRENT_SENSE,	PIN(A, 1),	GPIO_ANALOG)
-GPIO(PD3_CURRENT_SENSE,	PIN(A, 2),	GPIO_ANALOG)
-GPIO(PD1_VOLTAGE_SENSE,	PIN(A, 3),	GPIO_ANALOG)
-GPIO(PD2_VOLTAGE_SENSE,	PIN(A, 4),	GPIO_ANALOG)
-GPIO(PD3_VOLTAGE_SENSE,	PIN(A, 5),	GPIO_ANALOG)
-GPIO(VBUCK_IN_SENSE,	PIN(B, 0),	GPIO_ANALOG)
-GPIO(TEMP_SENSE,	PIN(B, 1),	GPIO_ANALOG)
+GPIO(VBIAS,		PIN(A, 4),	GPIO_ANALOG)
+GPIO(VOUT_1,		PIN(A, 5),	GPIO_ANALOG)
+GPIO(VOUT_2,		PIN(A, 6),	GPIO_ANALOG)
+
+/* Test points */
+GPIO(TP1,		PIN(B, 0),	GPIO_OUT_LOW)
+GPIO(TP2,		PIN(B, 1),	GPIO_OUT_LOW)
 
 /*
  * I2C pins should be configured as inputs until I2C module is
  * initialized. This will avoid driving the lines unintentionally.
  */
-GPIO(I2C1_SCL,		PIN(B, 8),	GPIO_INPUT)
-GPIO(I2C1_SDA,		PIN(B, 9),	GPIO_INPUT)
-GPIO(I2C2_SCL,		PIN(B, 13),	GPIO_INPUT)
-GPIO(I2C2_SDA,		PIN(B, 11), 	GPIO_INPUT)
-/* Mux select for I2C2 TCPCs */
-GPIO(I2C_MUX_SEL,	PIN(B, 2), 	GPIO_OUT_LOW)
+GPIO(I2C1_SCL,		PIN(B, 6),	GPIO_INPUT | GPIO_PULL_UP)
+GPIO(I2C1_SDA,		PIN(B, 7),	GPIO_INPUT | GPIO_PULL_UP)
+GPIO(I2C2_SCL,		PIN(A, 11),	GPIO_INPUT | GPIO_PULL_UP)
+GPIO(I2C2_SDA,		PIN(A, 12),	GPIO_INPUT | GPIO_PULL_UP)
 
-GPIO(BIAS_EN,		PIN(B, 10),	GPIO_OUT_HIGH)
-/* Primary-side communication GPIOs */
-GPIO(OPTO_IN,		PIN(B, 12),	GPIO_INPUT)
-GPIO(OPTO_OUT,		PIN(A, 8),	GPIO_OUT_LOW)
+/* Original I2C2 pins (invalid pin mux) on P0.9 boards */
+GPIO(GPIO_PB11,		PIN(B, 11),	GPIO_INPUT)
+GPIO(GPIO_PB12,		PIN(B, 12),	GPIO_INPUT)
 
 /* Unimplemented signals which we need to emulate for now */
 UNIMPLEMENTED(ENTERING_RW)
@@ -45,34 +40,15 @@ UNIMPLEMENTED(WP_L)
 
 /* Alternate functions */
 #if 0
+/* UART pins */
 GPIO(EC_UART_TX,	PIN(A, 9),	GPIO_OUT_LOW)
 GPIO(EC_UART_RX,	PIN(A, 10),	GPIO_INPUT)
-GPIO(DSPIC_UART_TX,	PIN(A, 14),	GPIO_OUT_LOW)
-GPIO(DSPIC_UART_RX,	PIN(A, 15),	GPIO_INPUT)
-
-/* WKUP6 */
-GPIO(WAKE,		PIN(B, 5),	GPIO_INPUT)
 #endif
 
-/* PWM outputs w/ negation */
-GPIO(PD1_PWM,		PIN(B, 14),	GPIO_OUT_LOW)
-GPIO(PD1_PWM_CMP,	PIN(B, 15),	GPIO_OUT_LOW)
-GPIO(PD2_PWM,		PIN(A, 6),	GPIO_OUT_LOW)
-GPIO(PD2_PWM_CMP,	PIN(B, 6),	GPIO_OUT_LOW)
-GPIO(PD3_PWM,		PIN(A, 7),	GPIO_OUT_LOW)
-GPIO(PD3_PWM_CMP,	PIN(B, 7),	GPIO_OUT_LOW)
+/* PB6 / PB7 I2C1_SCL / I2C1_SDA */
+ALTERNATE(PIN_MASK(B, 0x00C0), 1, MODULE_I2C,      GPIO_PULL_UP)
+/* PA11 / PA12 I2C2_SCL / I2C2_SDA */
+ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,      GPIO_PULL_UP)
 
-/* PB8 / PB9 / PB11: I2C1_SCL / I2C1_SDA / I2C2_SDA */
-ALTERNATE(PIN_MASK(B, 0x0B00), 1, MODULE_I2C,      0)
-/* PB13: I2C2_SCL */
-ALTERNATE(PIN_MASK(B, 0x2000), 5, MODULE_I2C,      0)
-/* PA9 / PA10 / PA14 / PA15: USART1 / USART2 */
-ALTERNATE(PIN_MASK(A, 0xC600), 1, MODULE_UART,     0)
-/* PA6 / PA7: TIM16_CH1 / TIM17_CH1 */
-ALTERNATE(PIN_MASK(A, 0x00C0), 5, MODULE_PWM, 0)
-/* PB6 / PB7: TIM16_CH1N / TIM17_CH1N */
-ALTERNATE(PIN_MASK(B, 0x00C0), 2, MODULE_PWM, 0)
-/* PB14: TIM15_CH1 */
-ALTERNATE(PIN_MASK(B, 0x4000), 1, MODULE_PWM, 0)
-/* PB15: TIM15_CH1N */
-ALTERNATE(PIN_MASK(B, 0x8000), 3, MODULE_PWM, 0)
+/* PA2 / PA9 / PA10: USART1 */
+ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,     0)
diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h
index c22855f046..246b4374cf 100644
--- a/chip/stm32/config-stm32f03x.h
+++ b/chip/stm32/config-stm32f03x.h
@@ -3,8 +3,15 @@
  * found in the LICENSE file.
  */
 
-/* Memory mapping */
+#ifdef CHIP_VARIANT_STM32F03X8
+#define CONFIG_FLASH_SIZE 0x00010000
+#define CONFIG_RAM_SIZE   0x00002000
+#else
 #define CONFIG_FLASH_SIZE 0x00008000
+#define CONFIG_RAM_SIZE   0x00001000
+#endif
+
+/* Memory mapping */
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0400  /* erase bank size */
 #define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
@@ -13,7 +20,6 @@
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
 
 #define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00001000
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
index f0d1fa85d1..f77fdf059e 100644
--- a/chip/stm32/config_chip.h
+++ b/chip/stm32/config_chip.h
@@ -18,6 +18,11 @@
 #define CONFIG_UART_CONSOLE 1
 
 /* Use variant specific configuration for flash / UART / IRQ */
+/* STM32F03X8 it itself a variant of STM32F03X with non-default flash sizes */
+#ifdef CHIP_VARIANT_STM32F03X8
+#define CHIP_VARIANT_STM32F03X
+#endif
+
 #if defined(CHIP_VARIANT_STM32L15X)
 #include "config-stm32l15x.h"
 #elif defined(CHIP_VARIANT_STM32L100)