Move board-specific GPIO lists to board-specific files

Signed-off-by: Randall Spangler <rspangler@chromium.org>

BUG=chrome-os-partner:7528
TEST=none

Change-Id: I47fd5d709a9575e41fdcdf21a7440ebbb762cef5

7 files changed, 233 insertions, 259 deletions

diff --git a/board/bds/board.c b/board/bds/board.c
index 82c599f834..e1120d4e41 100644
--- a/board/bds/board.c
+++ b/board/bds/board.c
@@ -1,13 +1,32 @@
-/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-/* Stellaris EKB-LM4F-EAC pins multiplexing */
+/* Stellaris EKB-LM4F-EAC board-specific configuration */
 
 #include "board.h"
+#include "gpio.h"
+#include "power_button.h"
 #include "registers.h"
 #include "util.h"
 
+
+/* GPIO signal list.  Must match order from enum gpio_signal. */
+const struct gpio_info gpio_list[GPIO_COUNT] = {
+	/* Inputs with interrupt handlers are first for efficiency */
+	{"POWER_BUTTONn", LM4_GPIO_C, (1<<5), GPIO_PULL_UP | GPIO_INT_BOTH,
+	 power_button_interrupt},
+	{"LID_SWITCHn",   LM4_GPIO_D, (1<<0), GPIO_PULL_UP | GPIO_INT_BOTH,
+	 power_button_interrupt},
+	/* Other inputs */
+	/* Outputs */
+	{"DEBUG_LED",    LM4_GPIO_A, (1<<7), GPIO_OUT_LOW, NULL},
+	/* Unimplemented outputs which we need to emulate for now */
+	GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_LID_SWITCHn"),
+	GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_PWRBTNn"),
+};
+
+
 void configure_board(void)
 {
 }
diff --git a/board/bds/board.h b/board/bds/board.h
index 2668b08b31..94a7af9484 100644
--- a/board/bds/board.h
+++ b/board/bds/board.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -53,6 +53,22 @@
 #define I2C_SPEED_CHARGER 100
 #define I2C_SPEED_THERMAL 400  /* TODO: TMP007 supports 3.4Mbps
 				  operation; use faster speed? */
+/* GPIO signal list */
+enum gpio_signal {
+	/* Inputs with interrupt handlers are first for efficiency */
+	GPIO_POWER_BUTTONn = 0,   /* Power button */
+	GPIO_LID_SWITCHn,         /* Lid switch */
+	/* Other inputs */
+	/* Outputs */
+	GPIO_DEBUG_LED,           /* Debug LED */
+	/* Signals which aren't implemented on BDS but we'll emulate anyway, to
+	 * make it more convenient to debug other code. */
+	GPIO_PCH_LID_SWITCHn,     /* Lid switch output to PCH */
+	GPIO_PCH_PWRBTNn,         /* Power button output to PCH */
+
+	/* Number of GPIOs; not an actual GPIO */
+	GPIO_COUNT
+};
 
 void configure_board(void);
 
diff --git a/board/link/board.c b/board/link/board.c
index e6c4faaeed..1b0b5a69cb 100644
--- a/board/link/board.c
+++ b/board/link/board.c
@@ -1,13 +1,80 @@
-/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-/* EC for Link mainboard pins multiplexing */
+/* EC for Link board configuration */
 
 #include "board.h"
+#include "gpio.h"
+#include "power_button.h"
 #include "registers.h"
 #include "util.h"
 
+
+/* GPIO signal list.  Must match order from enum gpio_signal. */
+const struct gpio_info gpio_list[GPIO_COUNT] = {
+	/* Inputs with interrupt handlers are first for efficiency */
+	{"POWER_BUTTONn",       LM4_GPIO_K, (1<<7), GPIO_INT_BOTH,
+	 power_button_interrupt},
+	{"LID_SWITCHn",         LM4_GPIO_K, (1<<5), GPIO_INT_BOTH,
+	 power_button_interrupt},
+	/* Other inputs */
+	{"POWER_ONEWIRE",       LM4_GPIO_H, (1<<2), 0, NULL},
+	{"THERMAL_DATA_READYn", LM4_GPIO_B, (1<<4), 0, NULL},
+	{"AC_PRESENT",          LM4_GPIO_H, (1<<3), 0, NULL},
+	{"PCH_BKLTEN",          LM4_GPIO_J, (1<<3), 0, NULL},
+	{"PCH_SLP_An",          LM4_GPIO_G, (1<<5), 0, NULL},
+	{"PCH_SLP_ME_CSW_DEVn", LM4_GPIO_G, (1<<4), 0, NULL},
+	{"PCH_SLP_S3n",         LM4_GPIO_J, (1<<0), 0, NULL},
+	{"PCH_SLP_S4n",         LM4_GPIO_J, (1<<1), 0, NULL},
+	{"PCH_SLP_S5n",         LM4_GPIO_J, (1<<2), 0, NULL},
+	{"PCH_SLP_SUSn",        LM4_GPIO_G, (1<<3), 0, NULL},
+	{"PCH_SUSWARNn",        LM4_GPIO_G, (1<<2), 0, NULL},
+	{"PGOOD_1_5V_DDR",      LM4_GPIO_K, (1<<0), 0, NULL},
+	{"PGOOD_1_5V_PCH",      LM4_GPIO_K, (1<<1), 0, NULL},
+	{"PGOOD_1_8VS",         LM4_GPIO_K, (1<<3), 0, NULL},
+	{"PGOOD_5VALW",         LM4_GPIO_H, (1<<0), 0, NULL},
+	{"PGOOD_CPU_CORE",      LM4_GPIO_M, (1<<3), 0, NULL},
+	{"PGOOD_VCCP",          LM4_GPIO_K, (1<<2), 0, NULL},
+	{"PGOOD_VCCSA",         LM4_GPIO_H, (1<<1), 0, NULL},
+	{"PGOOD_VGFX_CORE",     LM4_GPIO_D, (1<<2), 0, NULL},
+	{"RECOVERYn",           LM4_GPIO_H, (1<<7), 0, NULL},
+	{"USB1_STATUSn",        LM4_GPIO_E, (1<<7), 0, NULL},
+	{"USB2_STATUSn",        LM4_GPIO_E, (1<<1), 0, NULL},
+	{"WRITE_PROTECTn",      LM4_GPIO_J, (1<<4), 0, NULL},
+	/* Outputs; all unasserted by default */
+	{"CPU_PROCHOTn",        LM4_GPIO_F, (1<<2), GPIO_OUT_HIGH, NULL},
+	{"ENABLE_1_5V_DDR",     LM4_GPIO_H, (1<<5), GPIO_OUT_LOW, NULL},
+	{"ENABLE_BACKLIGHT",    LM4_GPIO_H, (1<<4), GPIO_OUT_LOW, NULL},
+	{"ENABLE_VCORE",        LM4_GPIO_F, (1<<7), GPIO_OUT_LOW, NULL},
+	{"ENABLE_VS",           LM4_GPIO_G, (1<<6), GPIO_OUT_LOW, NULL},
+	{"ENTERING_RW",         LM4_GPIO_J, (1<<5), GPIO_OUT_LOW, NULL},
+	{"PCH_A20GATE",         LM4_GPIO_Q, (1<<6), GPIO_OUT_LOW, NULL},
+	{"PCH_DPWROK",          LM4_GPIO_G, (1<<0), GPIO_OUT_LOW, NULL},
+	{"PCH_HDA_SDO",         LM4_GPIO_G, (1<<1), GPIO_OUT_LOW, NULL},
+	{"PCH_LID_SWITCHn",     LM4_GPIO_F, (1<<0), GPIO_OUT_HIGH, NULL},
+	{"PCH_NMIn",            LM4_GPIO_M, (1<<2), GPIO_OUT_HIGH, NULL},
+	{"PCH_PWRBTNn",         LM4_GPIO_G, (1<<7), GPIO_OUT_HIGH, NULL},
+	{"PCH_PWROK",           LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL},
+	{"PCH_RCINn",           LM4_GPIO_Q, (1<<7), GPIO_OUT_HIGH, NULL},
+	/* Exception: RSMRST# is asserted at power-on */
+	{"PCH_RSMRSTn",         LM4_GPIO_F, (1<<1), GPIO_OUT_LOW, NULL},
+	{"PCH_SMIn",            LM4_GPIO_F, (1<<4), GPIO_OUT_HIGH, NULL},
+	{"PCH_SUSACKn",         LM4_GPIO_F, (1<<3), GPIO_OUT_HIGH, NULL},
+	{"SHUNT_1_5V_DDR",      LM4_GPIO_F, (1<<6), GPIO_OUT_HIGH, NULL},
+	{"USB1_CTL1",           LM4_GPIO_E, (1<<2), GPIO_OUT_LOW, NULL},
+	{"USB1_CTL2",           LM4_GPIO_E, (1<<3), GPIO_OUT_LOW, NULL},
+	{"USB1_CTL3",           LM4_GPIO_E, (1<<4), GPIO_OUT_LOW, NULL},
+	{"USB1_ENABLE",         LM4_GPIO_E, (1<<5), GPIO_OUT_LOW, NULL},
+	{"USB1_ILIM_SEL",       LM4_GPIO_E, (1<<6), GPIO_OUT_LOW, NULL},
+	{"USB2_CTL1",           LM4_GPIO_D, (1<<4), GPIO_OUT_LOW, NULL},
+	{"USB2_CTL2",           LM4_GPIO_D, (1<<5), GPIO_OUT_LOW, NULL},
+	{"USB2_CTL3",           LM4_GPIO_D, (1<<6), GPIO_OUT_LOW, NULL},
+	{"USB2_ENABLE",         LM4_GPIO_D, (1<<7), GPIO_OUT_LOW, NULL},
+	{"USB2_ILIM_SEL",       LM4_GPIO_E, (1<<0), GPIO_OUT_LOW, NULL},
+};
+
+
 void configure_board(void)
 {
 }
diff --git a/board/link/board.h b/board/link/board.h
index 2295315b3a..430b8995b5 100644
--- a/board/link/board.h
+++ b/board/link/board.h
@@ -1,9 +1,9 @@
-/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* configuration for Link mainboard */
+/* Configuration for Link mainboard */
 
 #ifndef __BOARD_H
 #define __BOARD_H
@@ -54,6 +54,71 @@
 #define I2C_SPEED_THERMAL 400  /* TODO: TMP007 supports 3.4Mbps
 				  operation; use faster speed? */
 
+/* GPIO signal definitions. */
+enum gpio_signal {
+	/* Inputs with interrupt handlers are first for efficiency */
+	GPIO_POWER_BUTTONn = 0,   /* Power button */
+	GPIO_LID_SWITCHn,         /* Lid switch */
+	GPIO_POWER_ONEWIRE,       /* 1-wire interface to power adapter LEDs */
+	GPIO_THERMAL_DATA_READYn, /* Data ready from I2C thermal sensor */
+	/* Other inputs */
+	GPIO_AC_PRESENT,          /* AC power present */
+	GPIO_PCH_BKLTEN,          /* Backlight enable signal from PCH */
+	GPIO_PCH_SLP_An,          /* SLP_A# signal from PCH */
+	GPIO_PCH_SLP_ME_CSW_DEVn, /* SLP_ME_CSW_DEV# signal from PCH */
+	GPIO_PCH_SLP_S3n,         /* SLP_S3# signal from PCH */
+	GPIO_PCH_SLP_S4n,         /* SLP_S4# signal from PCH */
+	GPIO_PCH_SLP_S5n,         /* SLP_S5# signal from PCH */
+	GPIO_PCH_SLP_SUSn,        /* SLP_SUS# signal from PCH */
+	GPIO_PCH_SUSWARNn,        /* SUSWARN# signal from PCH */
+	GPIO_PGOOD_1_5V_DDR,      /* Power good on +1.5V_DDR */
+	GPIO_PGOOD_1_5V_PCH,      /* Power good on +1.5V_PCH */
+	GPIO_PGOOD_1_8VS,         /* Power good on +1.8VS */
+	GPIO_PGOOD_5VALW,         /* Power good on +5VALW */
+	GPIO_PGOOD_CPU_CORE,      /* Power good on +CPU_CORE */
+	GPIO_PGOOD_VCCP,          /* Power good on +VCCP */
+	GPIO_PGOOD_VCCSA,         /* Power good on +VCCSA */
+	GPIO_PGOOD_VGFX_CORE,     /* Power good on +VGFX_CORE */
+	GPIO_RECOVERYn,           /* Recovery signal from servo */
+	GPIO_USB1_STATUSn,        /* USB charger port 1 status output */
+	GPIO_USB2_STATUSn,        /* USB charger port 2 status output */
+	GPIO_WRITE_PROTECTn,      /* Write protect input */
+	/* Outputs */
+	GPIO_CPU_PROCHOTn,        /* Force CPU to think it's overheated */
+	GPIO_ENABLE_1_5V_DDR,     /* Enable +1.5V_DDR supply */
+	GPIO_ENABLE_BACKLIGHT,    /* Enable backlight power */
+	GPIO_ENABLE_VCORE,        /* Enable +CPU_CORE and +VGFX_CORE */
+	GPIO_ENABLE_VS,           /* Enable VS power supplies */
+	GPIO_ENTERING_RW,         /* Indicate when EC is entering RW code */
+	GPIO_PCH_A20GATE,         /* A20GATE signal to PCH */
+	GPIO_PCH_DPWROK,          /* DPWROK signal to PCH */
+	GPIO_PCH_HDA_SDO,         /* HDA_SDO signal to PCH; when high, ME
+				   * ignores security descriptor */
+	GPIO_PCH_LID_SWITCHn,     /* Lid switch output to PCH */
+	GPIO_PCH_NMIn,            /* Non-maskable interrupt pin to PCH */
+	GPIO_PCH_PWRBTNn,         /* Power button output to PCH */
+	GPIO_PCH_PWROK,           /* PWROK / APWROK signals to PCH */
+	GPIO_PCH_RCINn,           /* RCIN# signal to PCH */
+	GPIO_PCH_RSMRSTn,         /* Reset PCH resume power plane logic */
+	GPIO_PCH_SMIn,            /* System management interrupt to PCH */
+	GPIO_PCH_SUSACKn,         /* Acknowledge PCH SUSWARN# signal */
+	GPIO_SHUNT_1_5V_DDR,      /* Shunt +1.5V_DDR; may also enable +3V_TP
+				   * depending on stuffing. */
+	GPIO_USB1_CTL1,           /* USB charger port 1 CTL1 output */
+	GPIO_USB1_CTL2,           /* USB charger port 1 CTL2 output */
+	GPIO_USB1_CTL3,           /* USB charger port 1 CTL3 output */
+	GPIO_USB1_ENABLE,         /* USB charger port 1 enable */
+	GPIO_USB1_ILIM_SEL,       /* USB charger port 1 ILIM_SEL output */
+	GPIO_USB2_CTL1,           /* USB charger port 2 CTL1 output */
+	GPIO_USB2_CTL2,           /* USB charger port 2 CTL2 output */
+	GPIO_USB2_CTL3,           /* USB charger port 2 CTL3 output */
+	GPIO_USB2_ENABLE,         /* USB charger port 2 enable */
+	GPIO_USB2_ILIM_SEL,       /* USB charger port 2 ILIM_SEL output */
+
+	/* Number of GPIOs; not an actual GPIO */
+	GPIO_COUNT
+};
+
 void configure_board(void);
 
 #endif /* __BOARD_H */
diff --git a/chip/lm4/gpio.c b/chip/lm4/gpio.c
index f2c1b38b34..646f50107b 100644
--- a/chip/lm4/gpio.c
+++ b/chip/lm4/gpio.c
@@ -1,10 +1,11 @@
-/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* GPIO module for Chrome EC */
 
+#include "board.h"
 #include "console.h"
 #include "gpio.h"
 #include "power_button.h"
@@ -24,175 +25,15 @@ const uint32_t gpio_bases[] = {
 };
 
 
-/* Raw flags for GPIO_INFO */
-#define GI_OUTPUT      0x0001  /* Output */
-#define GI_PULL        0x0002  /* Input with on-chip pullup/pulldown */
-#define GI_HIGH        0x0004  /* If GI_OUTPUT, default high; if GI_PULL, pull
-				* up (otherwise default low / pull down) */
-#define GI_INT_RISING  0x0010  /* Interrupt on rising edge */
-#define GI_INT_FALLING 0x0020  /* Interrupt on falling edge */
-#define GI_INT_BOTH    0x0040  /* Interrupt on both edges */
-#define GI_INT_LOW     0x0080  /* Interrupt on low level */
-#define GI_INT_HIGH    0x0100  /* Interrupt on high level */
-/* Common flag combinations */
-#define GI_OUT_LOW     GI_OUTPUT
-#define GI_OUT_HIGH    (GI_OUTPUT | GI_HIGH)
-#define GI_PULL_DOWN   GI_PULL
-#define GI_PULL_UP     (GI_PULL | GI_HIGH)
-#define GI_INT_EDGE    (GI_INT_RISING | GI_INT_FALLING | GI_INT_BOTH)
-#define GI_INT_LEVEL   (GI_INT_LOW | GI_INT_HIGH)
-#define GI_INT_ANY     (GI_INT_EDGE | GI_INT_LEVEL)
-/* Note that if no flags are present, the signal is a high-Z input */
-
-struct gpio_info {
-	const char *name;
-	int port;   /* Port (LM4_GPIO_*) */
-	int mask;   /* Bitmask on that port (0x01 - 0x80; 0x00 =
-		       signal not implemented) */
-	uint32_t flags;   /* Flags (GI_*) */
-	void (*irq_handler)(enum gpio_signal signal);
-};
-
-/* Macro for signals which don't exist */
-#define SIGNAL_NOT_IMPLEMENTED(name) {name, LM4_GPIO_A, 0, 0, NULL}
-
-/* Signal information.  Must match order from enum gpio_signal. */
-#ifdef BOARD_link
-const struct gpio_info signal_info[GPIO_COUNT] = {
-	/* Inputs with interrupt handlers are first for efficiency */
-	{"POWER_BUTTONn",       LM4_GPIO_K, (1<<7), GI_INT_BOTH,
-	 power_button_interrupt},
-	{"LID_SWITCHn",         LM4_GPIO_K, (1<<5), GI_INT_BOTH,
-	 power_button_interrupt},
-	/* Other inputs */
-	{"POWER_ONEWIRE",       LM4_GPIO_H, (1<<2), 0, NULL},
-	{"THERMAL_DATA_READYn", LM4_GPIO_B, (1<<4), 0, NULL},
-	{"AC_PRESENT",          LM4_GPIO_H, (1<<3), 0, NULL},
-	{"PCH_BKLTEN",          LM4_GPIO_J, (1<<3), 0, NULL},
-	{"PCH_SLP_An",          LM4_GPIO_G, (1<<5), 0, NULL},
-	{"PCH_SLP_ME_CSW_DEVn", LM4_GPIO_G, (1<<4), 0, NULL},
-	{"PCH_SLP_S3n",         LM4_GPIO_J, (1<<0), 0, NULL},
-	{"PCH_SLP_S4n",         LM4_GPIO_J, (1<<1), 0, NULL},
-	{"PCH_SLP_S5n",         LM4_GPIO_J, (1<<2), 0, NULL},
-	{"PCH_SLP_SUSn",        LM4_GPIO_G, (1<<3), 0, NULL},
-	{"PCH_SUSWARNn",        LM4_GPIO_G, (1<<2), 0, NULL},
-	{"PGOOD_1_5V_DDR",      LM4_GPIO_K, (1<<0), 0, NULL},
-	{"PGOOD_1_5V_PCH",      LM4_GPIO_K, (1<<1), 0, NULL},
-	{"PGOOD_1_8VS",         LM4_GPIO_K, (1<<3), 0, NULL},
-	{"PGOOD_5VALW",         LM4_GPIO_H, (1<<0), 0, NULL},
-	{"PGOOD_CPU_CORE",      LM4_GPIO_M, (1<<3), 0, NULL},
-	{"PGOOD_VCCP",          LM4_GPIO_K, (1<<2), 0, NULL},
-	{"PGOOD_VCCSA",         LM4_GPIO_H, (1<<1), 0, NULL},
-	{"PGOOD_VGFX_CORE",     LM4_GPIO_D, (1<<2), 0, NULL},
-	{"RECOVERYn",           LM4_GPIO_H, (1<<7), 0, NULL},
-	{"USB1_STATUSn",        LM4_GPIO_E, (1<<7), 0, NULL},
-	{"USB2_STATUSn",        LM4_GPIO_E, (1<<1), 0, NULL},
-	{"WRITE_PROTECTn",      LM4_GPIO_J, (1<<4), 0, NULL},
-	/* Outputs; all unasserted by default */
-	{"CPU_PROCHOTn",        LM4_GPIO_F, (1<<2), GI_OUT_HIGH, NULL},
-	{"ENABLE_1_5V_DDR",     LM4_GPIO_H, (1<<5), GI_OUT_LOW, NULL},
-	{"ENABLE_BACKLIGHT",    LM4_GPIO_H, (1<<4), GI_OUT_LOW, NULL},
-	{"ENABLE_VCORE",        LM4_GPIO_F, (1<<7), GI_OUT_LOW, NULL},
-	{"ENABLE_VS",           LM4_GPIO_G, (1<<6), GI_OUT_LOW, NULL},
-	{"ENTERING_RW",         LM4_GPIO_J, (1<<5), GI_OUT_LOW, NULL},
-	{"PCH_A20GATE",         LM4_GPIO_Q, (1<<6), GI_OUT_LOW, NULL},
-	{"PCH_DPWROK",          LM4_GPIO_G, (1<<0), GI_OUT_LOW, NULL},
-	{"PCH_HDA_SDO",         LM4_GPIO_G, (1<<1), GI_OUT_LOW, NULL},
-	{"PCH_LID_SWITCHn",     LM4_GPIO_F, (1<<0), GI_OUT_HIGH, NULL},
-	{"PCH_NMIn",            LM4_GPIO_M, (1<<2), GI_OUT_HIGH, NULL},
-	{"PCH_PWRBTNn",         LM4_GPIO_G, (1<<7), GI_OUT_HIGH, NULL},
-	{"PCH_PWROK",           LM4_GPIO_F, (1<<5), GI_OUT_LOW, NULL},
-	{"PCH_RCINn",           LM4_GPIO_Q, (1<<7), GI_OUT_HIGH, NULL},
-	/* Exception: RSMRST# is asserted at power-on */
-	{"PCH_RSMRSTn",         LM4_GPIO_F, (1<<1), GI_OUT_LOW, NULL},
-	{"PCH_SMIn",            LM4_GPIO_F, (1<<4), GI_OUT_HIGH, NULL},
-	{"PCH_SUSACKn",         LM4_GPIO_F, (1<<3), GI_OUT_HIGH, NULL},
-	{"SHUNT_1_5V_DDR",      LM4_GPIO_F, (1<<6), GI_OUT_HIGH, NULL},
-	{"USB1_CTL1",           LM4_GPIO_E, (1<<2), GI_OUT_LOW, NULL},
-	{"USB1_CTL2",           LM4_GPIO_E, (1<<3), GI_OUT_LOW, NULL},
-	{"USB1_CTL3",           LM4_GPIO_E, (1<<4), GI_OUT_LOW, NULL},
-	{"USB1_ENABLE",         LM4_GPIO_E, (1<<5), GI_OUT_LOW, NULL},
-	{"USB1_ILIM_SEL",       LM4_GPIO_E, (1<<6), GI_OUT_LOW, NULL},
-	{"USB2_CTL1",           LM4_GPIO_D, (1<<4), GI_OUT_LOW, NULL},
-	{"USB2_CTL2",           LM4_GPIO_D, (1<<5), GI_OUT_LOW, NULL},
-	{"USB2_CTL3",           LM4_GPIO_D, (1<<6), GI_OUT_LOW, NULL},
-	{"USB2_ENABLE",         LM4_GPIO_D, (1<<7), GI_OUT_LOW, NULL},
-	{"USB2_ILIM_SEL",       LM4_GPIO_E, (1<<0), GI_OUT_LOW, NULL},
-};
-
-#else
-const struct gpio_info signal_info[GPIO_COUNT] = {
-	/* Inputs with interrupt handlers are first for efficiency */
-	{"POWER_BUTTONn", LM4_GPIO_C, (1<<5), GI_PULL_UP | GI_INT_BOTH,
-	 power_button_interrupt},
-	{"LID_SWITCHn",   LM4_GPIO_D, (1<<0), GI_PULL_UP | GI_INT_BOTH,
-	 power_button_interrupt},
-	SIGNAL_NOT_IMPLEMENTED("POWER_ONEWIRE"),
-	SIGNAL_NOT_IMPLEMENTED("THERMAL_DATA_READYn"),
-	/* Other inputs */
-	SIGNAL_NOT_IMPLEMENTED("AC_PRESENT"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_BKLTEN"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_SLP_An"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_SLP_ME_CSW_DEVn"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_SLP_S3n"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_SLP_S4n"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_SLP_S5n"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_SLP_SUSn"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_SUSWARNn"),
-	SIGNAL_NOT_IMPLEMENTED("PGOOD_1_5V_DDR"),
-	SIGNAL_NOT_IMPLEMENTED("PGOOD_1_5V_PCH"),
-	SIGNAL_NOT_IMPLEMENTED("PGOOD_1_8VS"),
-	SIGNAL_NOT_IMPLEMENTED("PGOOD_5VALW"),
-	SIGNAL_NOT_IMPLEMENTED("PGOOD_CPU_CORE"),
-	SIGNAL_NOT_IMPLEMENTED("PGOOD_VCCP"),
-	SIGNAL_NOT_IMPLEMENTED("PGOOD_VCCSA"),
-	SIGNAL_NOT_IMPLEMENTED("PGOOD_VGFX_CORE"),
-	SIGNAL_NOT_IMPLEMENTED("RECOVERYn"),
-	SIGNAL_NOT_IMPLEMENTED("USB1_STATUSn"),
-	SIGNAL_NOT_IMPLEMENTED("USB2_STATUSn"),
-	SIGNAL_NOT_IMPLEMENTED("WRITE_PROTECTn"),
-	/* Outputs */
-	SIGNAL_NOT_IMPLEMENTED("CPU_PROCHOTn"),
-	{"DEBUG_LED",    LM4_GPIO_A, (1<<7), GI_OUT_LOW, NULL},
-	SIGNAL_NOT_IMPLEMENTED("ENABLE_1_5V_DDR"),
-	SIGNAL_NOT_IMPLEMENTED("ENABLE_BACKLIGHT"),
-	SIGNAL_NOT_IMPLEMENTED("ENABLE_VCORE"),
-	SIGNAL_NOT_IMPLEMENTED("ENABLE_VS"),
-	SIGNAL_NOT_IMPLEMENTED("ENTERING_RW"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_A20GATE"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_DPWROK"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_HDA_SDO"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_LID_SWITCHn"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_NMIn"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_PWRBTNn"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_PWROK"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_RCINn"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_RSMRSTn"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_SMIn"),
-	SIGNAL_NOT_IMPLEMENTED("PCH_SUSACKn"),
-	SIGNAL_NOT_IMPLEMENTED("SHUNT_1_5V_DDR"),
-	SIGNAL_NOT_IMPLEMENTED("USB1_CTL1"),
-	SIGNAL_NOT_IMPLEMENTED("USB1_CTL2"),
-	SIGNAL_NOT_IMPLEMENTED("USB1_CTL3"),
-	SIGNAL_NOT_IMPLEMENTED("USB1_ENABLE"),
-	SIGNAL_NOT_IMPLEMENTED("USB1_ILIM_SEL"),
-	SIGNAL_NOT_IMPLEMENTED("USB2_CTL1"),
-	SIGNAL_NOT_IMPLEMENTED("USB2_CTL2"),
-	SIGNAL_NOT_IMPLEMENTED("USB2_CTL3"),
-	SIGNAL_NOT_IMPLEMENTED("USB2_ENABLE"),
-	SIGNAL_NOT_IMPLEMENTED("USB2_ILIM_SEL"),
-};
-
-#endif
-
-#undef SIGNAL_NOT_IMPLEMENTED
+/* Signal information from board.c.  Must match order from enum gpio_signal. */
+extern const struct gpio_info gpio_list[GPIO_COUNT];
 
 
 /* Find a GPIO signal by name.  Returns the signal index, or GPIO_COUNT if
  * no match. */
 static enum gpio_signal find_signal_by_name(const char *name)
 {
-	const struct gpio_info *g = signal_info;
+	const struct gpio_info *g = gpio_list;
 	int i;
 
 	if (!name || !*name)
@@ -223,7 +64,7 @@ static int find_gpio_port_index(uint32_t port_base)
 int gpio_pre_init(void)
 {
 	volatile uint32_t scratch  __attribute__((unused));
-	const struct gpio_info *g = signal_info;
+	const struct gpio_info *g = gpio_list;
 	int i;
 
 	/* Enable clocks to all the GPIO blocks (since we use all of them as
@@ -247,15 +88,15 @@ int gpio_pre_init(void)
 	for (i = 0; i < GPIO_COUNT; i++, g++) {
 
 		/* Handle GPIO direction */
-		if (g->flags & GI_OUTPUT) {
+		if (g->flags & GPIO_OUTPUT) {
 			/* Output with default level */
-			gpio_set_level(i, g->flags & GI_HIGH);
+			gpio_set_level(i, g->flags & GPIO_HIGH);
 			LM4_GPIO_DIR(g->port) |= g->mask;
 		} else {
 			/* Input */
-			if (g->flags & GI_PULL) {
+			if (g->flags & GPIO_PULL) {
 				/* With pull up/down */
-				if (g->flags & GI_HIGH)
+				if (g->flags & GPIO_HIGH)
 					LM4_GPIO_PUR(g->port) |= g->mask;
 				else
 					LM4_GPIO_PDR(g->port) |= g->mask;
@@ -266,13 +107,13 @@ int gpio_pre_init(void)
 		gpio_set_alternate_function(g->port, g->mask, 0);
 
 		/* Set up interrupts if necessary */
-		if (g->flags & GI_INT_LEVEL)
+		if (g->flags & GPIO_INT_LEVEL)
 			LM4_GPIO_IS(g->port) |= g->mask;
-		if (g->flags & (GI_INT_RISING | GI_INT_HIGH))
+		if (g->flags & (GPIO_INT_RISING | GPIO_INT_HIGH))
 			LM4_GPIO_IEV(g->port) |= g->mask;
-		if (g->flags & GI_INT_BOTH)
+		if (g->flags & GPIO_INT_BOTH)
 			LM4_GPIO_IBE(g->port) |= g->mask;
-		if (g->flags & GI_INT_ANY)
+		if (g->flags & GPIO_INT_ANY)
 			LM4_GPIO_IM(g->port) |= g->mask;
 	}
 
@@ -320,8 +161,8 @@ void gpio_set_alternate_function(int port, int mask, int func)
 
 int gpio_get_level(enum gpio_signal signal)
 {
-	return LM4_GPIO_DATA(signal_info[signal].port,
-			     signal_info[signal].mask) ? 1 : 0;
+	return LM4_GPIO_DATA(gpio_list[signal].port,
+			     gpio_list[signal].mask) ? 1 : 0;
 }
 
 
@@ -329,8 +170,8 @@ int gpio_set_level(enum gpio_signal signal, int value)
 {
 	/* Ok to write 0xff becuase LM4_GPIO_DATA bit-masks only the bit
 	 * we care about. */
-	LM4_GPIO_DATA(signal_info[signal].port,
-		      signal_info[signal].mask) = (value ? 0xff : 0);
+	LM4_GPIO_DATA(gpio_list[signal].port,
+		      gpio_list[signal].mask) = (value ? 0xff : 0);
 	return EC_SUCCESS;
 }
 
@@ -340,7 +181,7 @@ int gpio_set_level(enum gpio_signal signal, int value)
 static void gpio_interrupt(int port, uint32_t mis)
 {
 	int i = 0;
-	const struct gpio_info *g = signal_info;
+	const struct gpio_info *g = gpio_list;
 
 	for (i = 0; i < GPIO_COUNT; i++, g++) {
 		if (port == g->port && (mis & g->mask) && g->irq_handler)
@@ -365,7 +206,7 @@ DECLARE_IRQ(LM4_IRQ_GPIOC, __gpio_c_interrupt, 1);
 
 static int command_gpio_get(int argc, char **argv)
 {
-	const struct gpio_info *g = signal_info;
+	const struct gpio_info *g = gpio_list;
 	int i;
 
 	/* If a signal is specified, print only that one */
@@ -375,7 +216,7 @@ static int command_gpio_get(int argc, char **argv)
 			uart_puts("Unknown signal name.\n");
 			return EC_ERROR_UNKNOWN;
 		}
-		g = signal_info + i;
+		g = gpio_list + i;
 		uart_printf("  %d %s\n", gpio_get_level(i), g->name);
 		return EC_SUCCESS;
 	}
@@ -409,13 +250,13 @@ static int command_gpio_set(int argc, char **argv)
 		uart_puts("Unknown signal name.\n");
 		return EC_ERROR_UNKNOWN;
 	}
-	g = signal_info + i;
+	g = gpio_list + i;
 
 	if (!g->mask) {
 		uart_puts("Signal is not implemented.\n");
 		return EC_ERROR_UNKNOWN;
 	}
-	if (!(g->flags & GI_OUTPUT)) {
+	if (!(g->flags & GPIO_OUTPUT)) {
 		uart_puts("Signal is not an output.\n");
 		return EC_ERROR_UNKNOWN;
 	}
diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c
index 76a0732f9d..91b1c52b00 100644
--- a/chip/lm4/lpc.c
+++ b/chip/lm4/lpc.c
@@ -23,10 +23,9 @@ static void configure_gpio(void)
 	/* Set digital alternate function 15 for PL0:5, PM0:2, PM4:5 pins. */
 	/* I/O: PL0:3 = command/address/data
 	 * inp: PL4 (frame), PL5 (reset), PM0 (powerdown), PM5 (clock)
-	 * out: PM1 (sci), PM2 (clkrun), PM4 (serirq) */
-	/* TODO: PM2 is NMI#; not needed */
+	 * out: PM1 (sci), PM4 (serirq) */
 	gpio_set_alternate_function(LM4_GPIO_L, 0x3f, 0x0f);
-	gpio_set_alternate_function(LM4_GPIO_M, 0x37, 0x0f);
+	gpio_set_alternate_function(LM4_GPIO_M, 0x33, 0x0f);
 
 #ifdef BOARD_bds
 	/* Set the drive strength to 8mA for serirq only */
diff --git a/include/gpio.h b/include/gpio.h
index d8f270cf28..d3d0e27f3b 100644
--- a/include/gpio.h
+++ b/include/gpio.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,77 +8,44 @@
 #ifndef __CROS_EC_GPIO_H
 #define __CROS_EC_GPIO_H
 
+#include "board.h"  /* For board-dependent enum gpio_signal list */
 #include "common.h"
 
-/* GPIO signal definitions. */
-/* TODO: the exact list is board-depdendent */
-enum gpio_signal {
-	/* Inputs with interrupt handlers are first for efficiency */
-	GPIO_POWER_BUTTONn = 0,   /* Power button */
-	GPIO_LID_SWITCHn,         /* Lid switch */
-	GPIO_POWER_ONEWIRE,       /* 1-wire interface to power adapter LEDs */
-	GPIO_THERMAL_DATA_READYn, /* Data ready from I2C thermal sensor */
-	/* Other inputs */
-	GPIO_AC_PRESENT,          /* AC power present */
-	GPIO_PCH_BKLTEN,          /* Backlight enable signal from PCH */
-	GPIO_PCH_SLP_An,          /* SLP_A# signal from PCH */
-	GPIO_PCH_SLP_ME_CSW_DEVn, /* SLP_ME_CSW_DEV# signal from PCH */
-	GPIO_PCH_SLP_S3n,         /* SLP_S3# signal from PCH */
-	GPIO_PCH_SLP_S4n,         /* SLP_S4# signal from PCH */
-	GPIO_PCH_SLP_S5n,         /* SLP_S5# signal from PCH */
-	GPIO_PCH_SLP_SUSn,        /* SLP_SUS# signal from PCH */
-	GPIO_PCH_SUSWARNn,        /* SUSWARN# signal from PCH */
-	GPIO_PGOOD_1_5V_DDR,      /* Power good on +1.5V_DDR */
-	GPIO_PGOOD_1_5V_PCH,      /* Power good on +1.5V_PCH */
-	GPIO_PGOOD_1_8VS,         /* Power good on +1.8VS */
-	GPIO_PGOOD_5VALW,         /* Power good on +5VALW */
-	GPIO_PGOOD_CPU_CORE,      /* Power good on +CPU_CORE */
-	GPIO_PGOOD_VCCP,          /* Power good on +VCCP */
-	GPIO_PGOOD_VCCSA,         /* Power good on +VCCSA */
-	GPIO_PGOOD_VGFX_CORE,     /* Power good on +VGFX_CORE */
-	GPIO_RECOVERYn,           /* Recovery signal from servo */
-	GPIO_USB1_STATUSn,        /* USB charger port 1 status output */
-	GPIO_USB2_STATUSn,        /* USB charger port 2 status output */
-	GPIO_WRITE_PROTECTn,      /* Write protect input */
-	/* Outputs */
-	GPIO_CPU_PROCHOTn,        /* Force CPU to think it's overheated */
-#ifdef BOARD_bds
-	GPIO_DEBUG_LED,           /* Debug LED */
-#endif
-	GPIO_ENABLE_1_5V_DDR,     /* Enable +1.5V_DDR supply */
-	GPIO_ENABLE_BACKLIGHT,    /* Enable backlight power */
-	GPIO_ENABLE_VCORE,        /* Enable +CPU_CORE and +VGFX_CORE */
-	GPIO_ENABLE_VS,           /* Enable VS power supplies */
-	GPIO_ENTERING_RW,         /* Indicate when EC is entering RW code */
-	GPIO_PCH_A20GATE,         /* A20GATE signal to PCH */
-	GPIO_PCH_DPWROK,          /* DPWROK signal to PCH */
-	GPIO_PCH_HDA_SDO,         /* HDA_SDO signal to PCH; when high, ME
-				   * ignores security descriptor */
-	GPIO_PCH_LID_SWITCHn,     /* Lid switch output to PCH */
-	GPIO_PCH_NMIn,            /* Non-maskable interrupt pin to PCH */
-	GPIO_PCH_PWRBTNn,         /* Power button output to PCH */
-	GPIO_PCH_PWROK,           /* PWROK / APWROK signals to PCH */
-	GPIO_PCH_RCINn,           /* RCIN# signal to PCH */
-	GPIO_PCH_RSMRSTn,         /* Reset PCH resume power plane logic */
-	GPIO_PCH_SMIn,            /* System management interrupt to PCH */
-	GPIO_PCH_SUSACKn,         /* Acknowledge PCH SUSWARN# signal */
-	GPIO_SHUNT_1_5V_DDR,      /* Shunt +1.5V_DDR; may also enable +3V_TP
-				   * depending on stuffing. */
-	GPIO_USB1_CTL1,           /* USB charger port 1 CTL1 output */
-	GPIO_USB1_CTL2,           /* USB charger port 1 CTL2 output */
-	GPIO_USB1_CTL3,           /* USB charger port 1 CTL3 output */
-	GPIO_USB1_ENABLE,         /* USB charger port 1 enable */
-	GPIO_USB1_ILIM_SEL,       /* USB charger port 1 ILIM_SEL output */
-	GPIO_USB2_CTL1,           /* USB charger port 2 CTL1 output */
-	GPIO_USB2_CTL2,           /* USB charger port 2 CTL2 output */
-	GPIO_USB2_CTL3,           /* USB charger port 2 CTL3 output */
-	GPIO_USB2_ENABLE,         /* USB charger port 2 enable */
-	GPIO_USB2_ILIM_SEL,       /* USB charger port 2 ILIM_SEL output */
 
-	/* Number of GPIOs; not an actual GPIO */
-	GPIO_COUNT
+/* Flag definitions for gpio_info. */
+#define GPIO_OUTPUT      0x0001  /* Output */
+#define GPIO_PULL        0x0002  /* Input with on-chip pullup/pulldown */
+#define GPIO_HIGH        0x0004  /* If GPIO_OUTPUT, default high; if GPIO_PULL,
+				  * pull up (otherwise default low / pull
+				  * down) */
+#define GPIO_INT_RISING  0x0010  /* Interrupt on rising edge */
+#define GPIO_INT_FALLING 0x0020  /* Interrupt on falling edge */
+#define GPIO_INT_BOTH    0x0040  /* Interrupt on both edges */
+#define GPIO_INT_LOW     0x0080  /* Interrupt on low level */
+#define GPIO_INT_HIGH    0x0100  /* Interrupt on high level */
+/* Common flag combinations */
+#define GPIO_OUT_LOW     GPIO_OUTPUT
+#define GPIO_OUT_HIGH    (GPIO_OUTPUT | GPIO_HIGH)
+#define GPIO_PULL_DOWN   GPIO_PULL
+#define GPIO_PULL_UP     (GPIO_PULL | GPIO_HIGH)
+#define GPIO_INT_EDGE    (GPIO_INT_RISING | GPIO_INT_FALLING | GPIO_INT_BOTH)
+#define GPIO_INT_LEVEL   (GPIO_INT_LOW | GPIO_INT_HIGH)
+#define GPIO_INT_ANY     (GPIO_INT_EDGE | GPIO_INT_LEVEL)
+/* Note that if no flags are present, the signal is a high-Z input */
+
+/* GPIO signal definition structure, for use by board.c */
+struct gpio_info {
+	const char *name;
+	int port;         /* Port (LM4_GPIO_*) */
+	int mask;         /* Bitmask on that port (0x01 - 0x80; 0x00 =
+			   * signal not implemented) */
+	uint32_t flags;   /* Flags (GPIO_*) */
+	void (*irq_handler)(enum gpio_signal signal);
 };
 
+/* Macro for signals which don't exist */
+#define GPIO_SIGNAL_NOT_IMPLEMENTED(name) {name, LM4_GPIO_A, 0, 0, NULL}
+
 
 /* Pre-initializes the module.  This occurs before clocks or tasks are
  * set up. */