cleanup: Remove CDRAM / CODERAM CONFIGs

CDRAM / CODERAM configs were previously used for chips which copied code
from external SPI to program memory prior to execution, and were used
inconsistently between npcx and mec1322.

These CONFIGs are now completely redundant given new configs like
CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE.

BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4
Reviewed-on: https://chromium-review.googlesource.com/297804
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>

16 files changed, 38 insertions, 78 deletions

diff --git a/board/npcx_evb/board.h b/board/npcx_evb/board.h
index 7f1b3529a4..bebdbb6a11 100644
--- a/board/npcx_evb/board.h
+++ b/board/npcx_evb/board.h
@@ -8,9 +8,6 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
-/* Support Code RAM architecture (Run code in RAM) */
-#define CONFIG_CODERAM_ARCH
-
 /* Optional modules */
 #define CONFIG_ADC
 #define CONFIG_PECI
diff --git a/board/npcx_evb_arm/board.h b/board/npcx_evb_arm/board.h
index 4c795059ac..e9ccaea25b 100644
--- a/board/npcx_evb_arm/board.h
+++ b/board/npcx_evb_arm/board.h
@@ -8,9 +8,6 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
-/* Support Code RAM architecture (Run code in RAM) */
-#define CONFIG_CODERAM_ARCH
-
 /* Optional modules */
 #define CONFIG_ADC
 #define CONFIG_PWM
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h
index 514f292914..2309baad60 100644
--- a/chip/mec1322/config_chip.h
+++ b/chip/mec1322/config_chip.h
@@ -100,7 +100,6 @@
 
 /* Program memory base address */
 #define CONFIG_PROGRAM_MEMORY_BASE	0x00100000
-#define CONFIG_CDRAM_BASE		0x00100000
 
 #include "config_flash_layout.h"
 
diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h
index 4a10175a02..0efa9d8345 100644
--- a/chip/mec1322/config_flash_layout.h
+++ b/chip/mec1322/config_flash_layout.h
@@ -15,7 +15,6 @@
  */
 
 /* Non-memmapped, external SPI */
-#define CONFIG_CODERAM_ARCH
 #define CONFIG_EXTERNAL_STORAGE
 #undef  CONFIG_MAPPED_STORAGE
 #undef  CONFIG_FLASH_PSTATE
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h
index 56db32cc65..17e366ccfd 100644
--- a/chip/npcx/config_chip.h
+++ b/chip/npcx/config_chip.h
@@ -47,8 +47,6 @@
 /* Memory mapping */
 #define CONFIG_RAM_BASE            0x200C0000 /* memory address of data ram */
 #define CONFIG_RAM_SIZE            (0x00008000 - 0x800) /* 30KB data ram */
-#define CONFIG_CDRAM_BASE          0x100A8000 /* memory address of code ram */
-#define CONFIG_CDRAM_SIZE          0x00018000 /* 96KB code ram */
 #define CONFIG_PROGRAM_MEMORY_BASE 0x64000000 /* program memory base address */
 #define CONFIG_LPRAM_BASE          0x40001600 /* memory address of lpwr ram */
 #define CONFIG_LPRAM_SIZE	   0x00000620 /* 1568B low power ram */
diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h
index 986c0bbfea..9710d2b1e5 100644
--- a/chip/npcx/config_flash_layout.h
+++ b/chip/npcx/config_flash_layout.h
@@ -35,14 +35,14 @@
 
 /* RO firmware offset in flash */
 #define CONFIG_RO_MEM_OFF	CONFIG_RO_HDR_SIZE
-#define CONFIG_RO_SIZE		CONFIG_CDRAM_SIZE    /* 96KB for RO FW */
+#define CONFIG_RO_SIZE		(96 * 1024)   /* 96KB for RO FW */
 #define CONFIG_FLASH_SIZE	CONFIG_FLASH_PHYSICAL_SIZE
 
 /* RW firmware offset in flash */
 #define CONFIG_RW_MEM_OFF	CONFIG_RW_STORAGE_OFF
-#define CONFIG_RW_SIZE		CONFIG_CDRAM_SIZE    /* 96KB for RW FW */
+#define CONFIG_RW_SIZE		(96 * 1024)   /* 96KB for RW FW */
 
-/* The storage offset of ec.R*.flat which is used for CONFIG_CDRAM_ARCH */
+/* The storage offset of ec.R*.flat */
 #define CONFIG_RO_STORAGE_OFF	0
 #define CONFIG_RW_STORAGE_OFF	CONFIG_FW_IMAGE_SIZE /* 128 KB alignemnt */
 
diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c
index c97c2b38cc..2bdcefe8a2 100644
--- a/chip/npcx/flash.c
+++ b/chip/npcx/flash.c
@@ -23,7 +23,7 @@ uint8_t flag_prot_inconsistent;
 
 #define FLASH_ABORT_TIMEOUT     10000
 
-#ifdef CONFIG_CODERAM_ARCH
+#ifdef CONFIG_EXTERNAL_STORAGE
 #define TRISTATE_FLASH(x)
 #else
 #define TRISTATE_FLASH(x) flash_tristate(x)
@@ -770,7 +770,7 @@ int flash_pre_init(void)
 	/* Enable FIU interface */
 	flash_pinmux(1);
 
-#ifdef CONFIG_CODERAM_ARCH
+#ifdef CONFIG_EXTERNAL_STORAGE
 	/* Disable tristate all the time */
 	CLEAR_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
 #endif
diff --git a/chip/npcx/header.c b/chip/npcx/header.c
index ff0c50eb3b..49b7488b4f 100644
--- a/chip/npcx/header.c
+++ b/chip/npcx/header.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,9 @@
  */
 
 #include <stdint.h>
+
+#include "config.h"
 #include "registers.h"
-#include "config_chip.h"
 
 /* Signature used by fw header */
 #define SIG_FW_EC           0x2A3B4D5E
@@ -24,7 +25,8 @@
 #define ERROR_DETECTION_DIS 0x00
 
 /* Code RAM addresses use by header */
-#define FW_START_ADDR  CONFIG_CDRAM_BASE /* Put FW at the begin of CODE RAM   */
+/* Put FW at the begin of CODE RAM */
+#define FW_START_ADDR  CONFIG_PROGRAM_MEMORY_BASE
 
 /* TODO: It will be filled automatically by ECST */
 /* The entry point of reset handler (filled by ECST tool)*/
diff --git a/chip/npcx/spiflashfw/ec_npcxflash.c b/chip/npcx/spiflashfw/ec_npcxflash.c
index cc97f69e5a..ef62ac97dc 100644
--- a/chip/npcx/spiflashfw/ec_npcxflash.c
+++ b/chip/npcx/spiflashfw/ec_npcxflash.c
@@ -6,8 +6,10 @@
  */
 
 #include <stdint.h>
+
+#include "config.h"
 #include "registers.h"
-#include "config_chip.h"
+#include "util.h"
 
 /*****************************************************************************/
 /* spi flash internal functions */
@@ -241,7 +243,7 @@ int sspi_flash_verify(int offset, int size, const char *data)
 int sspi_flash_get_image_used(const char *fw_base)
 {
 	const uint8_t *image;
-	int size = CONFIG_CDRAM_SIZE; /* maximum size is 128KB */
+	int size = MAX(CONFIG_RO_SIZE, CONFIG_RW_SIZE); /* max size is 128KB */
 
 	image = (const uint8_t *)fw_base;
 	/*
@@ -265,7 +267,7 @@ sspi_flash_upload(int spi_offset, int spi_size)
 	/*
 	 * Flash image has been uploaded to Code RAM
 	 */
-	const char *image_base = (const char *)CONFIG_CDRAM_BASE;
+	const char *image_base = (const char *)CONFIG_PROGRAM_MEMORY_BASE;
 	uint32_t sz_image = spi_size;
 
 	/* Unlock & stop watchdog */
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index 23d66d7882..b6c23396b2 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -690,7 +690,7 @@ DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE,
 		system_rtc_set_value,
 		EC_VER_MASK(0));
 
-#ifdef CONFIG_CODERAM_ARCH
+#ifdef CONFIG_EXTERNAL_STORAGE
 void system_jump_to_booter(void)
 {
 	enum API_RETURN_STATUS_T status;
@@ -709,11 +709,11 @@ void system_jump_to_booter(void)
 
 	/* Make sure the reset vector is inside the destination image */
 	addr_entry = *(uintptr_t *)(flash_offset +
-				    CONFIG_PROGRAM_MEMORY_BASE + 4);
+				    CONFIG_MAPPED_STORAGE_BASE + 4);
 
 	download_from_flash(
 		flash_offset,      /* The offset of the data in spi flash */
-		CONFIG_CDRAM_BASE, /* The address of the downloaded data  */
+		CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */
 		flash_used,        /* Number of bytes to download      */
 		SIGN_NO_CHECK,     /* Need CRC check or not               */
 		addr_entry,        /* jump to this address after download */
diff --git a/common/flash.c b/common/flash.c
index 0f45b8e4d5..b2c3847e60 100644
--- a/common/flash.c
+++ b/common/flash.c
@@ -115,7 +115,7 @@ int flash_range_ok(int offset, int size_req, int align)
  */
 static const char *flash_physical_dataptr(int offset)
 {
-	return (char *)((uintptr_t)CONFIG_PROGRAM_MEMORY_BASE + offset);
+	return (char *)((uintptr_t)CONFIG_MAPPED_STORAGE_BASE + offset);
 }
 
 int flash_dataptr(int offset, int size_req, int align, const char **ptrp)
diff --git a/common/fmap.c b/common/fmap.c
index 28800ee663..4fbafe6f91 100644
--- a/common/fmap.c
+++ b/common/fmap.c
@@ -21,12 +21,8 @@
  * variable), this computes the offset to the start of the image on flash.
  */
 
-#ifdef NPCX_RO_HEADER
-#define RELATIVE_RO(addr) ((addr) - CONFIG_CDRAM_BASE)
-#else
 #define RELATIVE_RO(addr) ((addr) - CONFIG_PROGRAM_MEMORY_BASE - \
 			   CONFIG_RO_MEM_OFF)
-#endif
 
 struct fmap_header {
 	char        fmap_signature[FMAP_SIGNATURE_SIZE];
diff --git a/common/system.c b/common/system.c
index d617aa39f1..690403a94f 100644
--- a/common/system.c
+++ b/common/system.c
@@ -95,7 +95,7 @@ uint32_t sleep_mask;
 
 /**
  * Return the program memory address where the image `copy` begins or should
- * begin. In the case of CODERAM_ARCH, the image may or may not currently
+ * begin. In the case of external storage, the image may or may not currently
  * reside at the location returned.
  */
 static uintptr_t get_program_memory_addr(enum system_image_copy_t copy)
@@ -314,8 +314,8 @@ void system_disable_jump(void)
 
 test_mockable enum system_image_copy_t system_get_image_copy(void)
 {
-#ifdef CONFIG_CODERAM_ARCH
-	/* Return which region is used in Code RAM */
+#ifdef CONFIG_EXTERNAL_STORAGE
+	/* Return which region is used in program memory */
 	return system_get_shrspi_image_copy();
 #else
 	uintptr_t my_addr = (uintptr_t)system_get_image_copy -
@@ -335,7 +335,7 @@ test_mockable enum system_image_copy_t system_get_image_copy(void)
 
 int system_get_image_used(enum system_image_copy_t copy)
 {
-#if !defined(CONFIG_MAPPED_STORAGE) && defined(CONFIG_CODERAM_ARCH)
+#ifndef CONFIG_MAPPED_STORAGE
 	int image_offset;
 	uint8_t buf[SPI_FLASH_MAX_WRITE_SIZE];
 #endif
@@ -350,7 +350,7 @@ int system_get_image_used(enum system_image_copy_t copy)
 	 * last byte of the image.  See ec.lds.S for how this is inserted at
 	 * the end of the image.
 	 */
-#if !defined(CONFIG_MAPPED_STORAGE) && defined(CONFIG_CODERAM_ARCH)
+#ifndef CONFIG_MAPPED_STORAGE
 	image_offset = (copy == SYSTEM_IMAGE_RW) ? CONFIG_RW_STORAGE_OFF :
 			CONFIG_RO_STORAGE_OFF;
 	image = buf;
@@ -502,8 +502,8 @@ int system_run_image_copy(enum system_image_copy_t copy)
 	if (base == 0xffffffff)
 		return EC_ERROR_INVAL;
 
-#ifdef CONFIG_CODERAM_ARCH
-	/* Jump to little FW for code ram architecture */
+#ifdef CONFIG_EXTERNAL_STORAGE
+	/* Jump to loader */
 	init_addr = system_get_lfw_address();
 
 	system_set_image_copy(copy);
@@ -538,7 +538,7 @@ int system_run_image_copy(enum system_image_copy_t copy)
 
 const char *system_get_version(enum system_image_copy_t copy)
 {
-#if !defined(CONFIG_MAPPED_STORAGE) && defined(CONFIG_CODERAM_ARCH)
+#ifndef CONFIG_MAPPED_STORAGE
 	static struct version_struct vdata;
 #endif
 
@@ -559,32 +559,18 @@ const char *system_get_version(enum system_image_copy_t copy)
 	 */
 	addr = ((uintptr_t)&version_data -
 	       get_program_memory_addr(active_copy));
-#ifdef CONFIG_CODERAM_ARCH
-#ifdef CONFIG_MAPPED_STORAGE
-	/* Geometry constants have non-standard meaning for npcx */
-	addr = ((uintptr_t)&version_data - CONFIG_CDRAM_BASE +
-			   get_program_memory_addr(copy));
-#else
+
 	/*
-	 * Since our requested image isn't currently populated in program
-	 * memory, read the version information from the proper location
+	 * Read the version information from the proper location
 	 * on storage.
 	 */
 	addr += (copy == SYSTEM_IMAGE_RW) ? CONFIG_RW_STORAGE_OFF :
 					    CONFIG_RO_STORAGE_OFF;
-#endif /* CONFIG_MAPPED_STORAGE */
-#else /* CONFIG_CODERAM_ARCH */
-	/*
-	 * Read version from program memory, which is always populated with
-	 * both images.
-	 */
-	addr += get_program_memory_addr(copy);
-#endif /*CONFIG_CODERAM_ARCH */
 
-#if defined(CONFIG_MAPPED_STORAGE) || !defined(CONFIG_CODERAM_ARCH)
-	/* Directly access the data from program memory or mapped flash. */
+#ifdef CONFIG_MAPPED_STORAGE
 	v = (const struct version_struct *)addr;
 #else
+
 	/* Read the version struct from flash into a buffer. */
 	if (flash_read(addr, sizeof(vdata), (char *)&vdata))
 		return "";
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S
index 6e5eefba32..7fcf6f0adc 100644
--- a/core/cortex-m/ec.lds.S
+++ b/core/cortex-m/ec.lds.S
@@ -31,18 +31,11 @@ MEMORY
 #endif
     FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION)
     IRAM (rw)  : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE
-#ifdef CONFIG_CODERAM_ARCH
-#ifdef CONFIG_MAPPED_STORAGE
-   /* Geometry constants have non-standard meaning for npcx */
+#ifdef CONFIG_EXTERNAL_STORAGE
    CDRAM (rx) : \
-        ORIGIN = CONFIG_CDRAM_BASE, \
-        LENGTH = CONFIG_CDRAM_SIZE
-#else /* CONFIG_MAPPED_STORAGE */
-   CDRAM (rx) : \
-        ORIGIN = CONFIG_CDRAM_BASE + FW_MEM_OFF(SECTION), \
+        ORIGIN = CONFIG_PROGRAM_MEMORY_BASE + FW_MEM_OFF(SECTION), \
         LENGTH = FW_SIZE(SECTION)
-#endif /* CONFIG_MAPPED_STORAGE */
-#endif /* CONFIG_CODERAM_ARCH */
+#endif /* CONFIG_EXTERNAL_STORAGE */
 #ifdef RSA_PUBLIC_KEY_SIZE
     PSTATE(r)  : \
         ORIGIN = FW_OFF(SECTION) + FW_SIZE(SECTION), \
@@ -85,7 +78,7 @@ SECTIONS
 #endif
         OUTDIR/core/CORE/init.o (.text)
         *(.text*)
-#ifdef CONFIG_CODERAM_ARCH
+#ifdef CONFIG_EXTERNAL_STORAGE
         __flash_lpfw_start = .;
         /* Entering deep idle FW for better power consumption */
         KEEP(*(.lowpower_ram))
@@ -200,7 +193,7 @@ SECTIONS
         KEEP(*(.google))
 #endif
         . = ALIGN(4);
-#ifdef CONFIG_CODERAM_ARCH
+#ifdef CONFIG_EXTERNAL_STORAGE
     } > CDRAM AT > FLASH
 #else
     } > FLASH
@@ -229,7 +222,7 @@ SECTIONS
         . = ALIGN(4);
         __bss_end = .;
     } > IRAM
-#ifdef CONFIG_CODERAM_ARCH
+#ifdef CONFIG_EXTERNAL_STORAGE
     .data : AT(LOADADDR(.rodata) + SIZEOF(.rodata)) {
 #else
     .data : AT(ADDR(.rodata) + SIZEOF(.rodata)) {
diff --git a/include/config.h b/include/config.h
index 248c7c4813..f73773e416 100644
--- a/include/config.h
+++ b/include/config.h
@@ -496,15 +496,6 @@
 
 /*****************************************************************************/
 
-/* Support Code RAM architecture (run code in RAM). */
-#undef CONFIG_CODERAM_ARCH
-
-/* Base address of Code RAM. */
-#undef CONFIG_CDRAM_BASE
-
-/* Size of Code RAM. */
-#undef CONFIG_CDRAM_SIZE
-
 /* Provide common core code to output panic information without interrupts. */
 #define CONFIG_COMMON_PANIC_OUTPUT
 
diff --git a/include/system.h b/include/system.h
index e1bb43da93..6767c30a10 100644
--- a/include/system.h
+++ b/include/system.h
@@ -372,7 +372,7 @@ void system_set_rtc_alarm(uint32_t seconds, uint32_t microseconds);
  */
 void system_reset_rtc_alarm(void);
 
-#ifdef CONFIG_CODERAM_ARCH
+#ifdef CONFIG_EXTERNAL_STORAGE
 /**
  * Return address of little FW to prepare for sysjump
  *