diff options
author | Tommy Chung <tommy.chung@quanta.corp-partner.google.com> | 2022-04-21 10:20:48 +0800 |
---|---|---|
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-04-27 03:52:50 +0000 |
commit | d90cb450f5955a06a830ce90fd75afea35060238 (patch) | |
tree | 1f668129e36a1b1e52ca4a3f12261165d2569c6f | |
parent | d9bde0e5381d7facfbaf9bebd08a14931213a969 (diff) | |
download | chrome-ec-d90cb450f5955a06a830ce90fd75afea35060238.tar.gz |
rt1718s: Set VCONN_OCP_SEL to 400mA
Since there's +/-10% tolerance in VCONN OCP level, which leads to
unstable output of VCONN and sometimes OCP will be around only 200mA
(the loading spec should be 300mA), set VCONN_OCP_SEL to 400mA to
avoid this scenario.
BUG=b:223537765
BRANCH=cherry
TEST=make sure that VCONN OCP will not drop below 300mA.
Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com>
Change-Id: Ie08a465fc819dc9d8548f356937ca8f7be90d0ca
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3596383
Reviewed-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-by: Eric Yilun Lin <yllin@google.com>
-rw-r--r-- | driver/tcpm/rt1718s.c | 4 | ||||
-rw-r--r-- | driver/tcpm/rt1718s.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/driver/tcpm/rt1718s.c b/driver/tcpm/rt1718s.c index 4abc2b06b8..3211bacb03 100644 --- a/driver/tcpm/rt1718s.c +++ b/driver/tcpm/rt1718s.c @@ -229,6 +229,10 @@ static int rt1718s_init(int port) RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL, RT1718S_VBUS_VOL_TO_REG(20))); + /* Set VCONN_OCP_SEL to 400mA */ + RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCONN_CONTROL_3, + RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL, 0x7F)); + /* Disable FOD function */ RETURN_ERROR(rt1718s_update_bits8(port, 0xCF, 0x40, 0x00)); diff --git a/driver/tcpm/rt1718s.h b/driver/tcpm/rt1718s.h index 2df05bcb2e..04650cdffd 100644 --- a/driver/tcpm/rt1718s.h +++ b/driver/tcpm/rt1718s.h @@ -37,6 +37,7 @@ #define RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 BIT(7) #define RT1718S_VCONN_CONTROL_2_OVP_EN_CC2 BIT(6) #define RT1718S_VCONN_CONTROL_3 0x8C +#define RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL GENMASK(7, 5) #define RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG BIT(1) #define RT1718S_SYS_CTRL2 0x90 |