ap_pwrseq: Re-arrange signal handling in power state G3S5

Move SLP_SUS_L checking to chipset specific file because not all have
SLP_SUS_L signal.

BUG=none
BRANCH=none
TEST=build nivviks; flash, power on successfully; test AP shutdown,
system enter S5 then G3; then press power button to bring system back to
S0 and AP is running.

Signed-off-by: Li Feng <li1.feng@intel.com>
Change-Id: I580b19499f472a199319359a251ba19a66b4838a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3622494
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Commit-Queue: Andrew McRae <amcrae@google.com>
Reviewed-by: Andrew McRae <amcrae@google.com>

3 files changed, 37 insertions, 40 deletions

diff --git a/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h b/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h
index 1832c4877c..93966c4782 100644
--- a/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h
+++ b/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h
@@ -22,7 +22,8 @@
 #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(PWR_DSW_PWROK)
 #define IN_ALL_S0_MASK (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP)
 #define IN_ALL_S0_VALUE IN_PGOOD_ALL_CORE
-#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
+#define PWRSEQ_G3S5_UP_SIGNAL IN_PCH_SLP_SUS
+#define PWRSEQ_G3S5_UP_VALUE 0
 
 #else
 #warning("Input power signals state flags not defined");
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c
index 3280aaec35..2f92e53fd0 100644
--- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c
@@ -15,6 +15,23 @@ void ap_off(void)
 	power_signal_set(PWR_EC_PCH_SYS_PWROK, 0);
 }
 
+static int check_pch_out_of_suspend(void)
+{
+	int ret;
+	/*
+	 * Wait for SLP_SUS deasserted.
+	 */
+	ret = power_wait_mask_signals_timeout(IN_PCH_SLP_SUS,
+					      0,
+					      IN_PCH_SLP_SUS_WAIT_TIME_MS);
+	if (ret == 0) {
+		LOG_DBG("SLP_SUS now %d", power_signal_get(PWR_SLP_SUS));
+		return 1;
+	}
+	LOG_ERR("wait SLP_SUS deassertion timeout");
+	return 0; /* timeout */
+}
+
 /* Handle ALL_SYS_PWRGD signal
  * This will be overridden if the custom signal handler is needed
  */
@@ -156,6 +173,19 @@ void s0s3_action_handler(void)
 	ap_off();
 }
 
+enum power_states_ndsx g3s5_action_handler(void)
+{
+	/*
+	 * Now wait for SLP_SUS_L to go high based on tPCH32. If this
+	 * signal doesn't go high within 250 msec then go back to G3.
+	 */
+	if (check_pch_out_of_suspend()) {
+		ap_power_ev_send_callbacks(AP_POWER_PRE_INIT);
+		return SYS_POWER_STATE_G3S5;
+	}
+	return SYS_POWER_STATE_S5G3;
+}
+
 void init_chipset_pwr_seq_state(void)
 {
 	/* Deassert reset pin */
@@ -262,6 +292,7 @@ enum power_states_ndsx chipset_pwr_sm_run(enum power_states_ndsx curr_state)
 	switch (curr_state) {
 	case SYS_POWER_STATE_G3S5:
 		board_ap_power_action_g3_s5();
+		curr_state = g3s5_action_handler();
 		break;
 	case SYS_POWER_STATE_S5:
 		break;
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c
index 2308867177..a54de0a81d 100644
--- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c
@@ -130,25 +130,6 @@ int rsmrst_power_is_good(void)
 	return power_signal_get(PWR_RSMRST);
 }
 
-int check_pch_out_of_suspend(void)
-{
-	int ret;
-
-	/*
-	 * Wait for SLP_SUS deasserted.
-	 */
-	ret = power_wait_mask_signals_timeout(IN_PCH_SLP_SUS,
-					      0,
-					      IN_PCH_SLP_SUS_WAIT_TIME_MS);
-
-	if (ret == 0) {
-		LOG_DBG("SLP_SUS now %d", power_signal_get(PWR_SLP_SUS));
-		return 1;
-	}
-	LOG_ERR("wait SLP_SUS deassertion timeout");
-	return 0; /* timeout */
-}
-
 /* Handling RSMRST signal is mostly common across x86 chipsets */
 void rsmrst_pass_thru_handler(void)
 {
@@ -165,10 +146,6 @@ void rsmrst_pass_thru_handler(void)
 	}
 }
 
-/* TODO:
- * Add power down sequence
- * Add S0ix
- */
 static int common_pwr_sm_run(int state)
 {
 	switch (state) {
@@ -181,19 +158,11 @@ static int common_pwr_sm_run(int state)
 		break;
 
 	case SYS_POWER_STATE_G3S5:
-		if (power_wait_signals_timeout(
-			IN_PGOOD_ALL_CORE,
-			AP_PWRSEQ_DT_VALUE(wait_signal_timeout)))
-			break;
-		/*
-		 * Now wait for SLP_SUS_L to go high based on tPCH32. If this
-		 * signal doesn't go high within 250 msec then go back to G3.
-		 */
-		if (check_pch_out_of_suspend()) {
-			ap_power_ev_send_callbacks(AP_POWER_PRE_INIT);
+		if ((power_get_signals() & PWRSEQ_G3S5_UP_SIGNAL) ==
+				PWRSEQ_G3S5_UP_VALUE)
 			return SYS_POWER_STATE_S5;
-		}
-		return SYS_POWER_STATE_S5G3;
+		else
+			return SYS_POWER_STATE_S5G3;
 
 	case SYS_POWER_STATE_S5:
 		/* In S5 make sure no more signal lost */
@@ -201,10 +170,6 @@ static int common_pwr_sm_run(int state)
 		if (check_power_rails_enabled() && rsmrst_power_is_good()) {
 			/* rsmrst is intact */
 			rsmrst_pass_thru_handler();
-			if (power_signals_on(IN_PCH_SLP_SUS)) {
-				k_timer_stop(&s5_inactive_timer);
-				return SYS_POWER_STATE_S5G3;
-			}
 			if (signals_valid_and_off(IN_PCH_SLP_S5)) {
 				k_timer_stop(&s5_inactive_timer);
 				return SYS_POWER_STATE_S5S4;