npcx: eSPI: workaround the issue in NPCX99nF errata rev1_2, No.3.10.

Enabling an eSPI channel (r.g. Peripheral Channel, Virtual Wire Channel,
etc.) during an eSPI transaction might (with low probability) cause the
eSPI_SIF module to transition to a wrong state and therefore respond
with FATAL_ERROR on an incoming transaction.
This CL workarounds this issue by clearing the bit 4 of NPCX eSPI
specific register#2.

This workaround should be also applied to NPCX7 (except npcx7m6f).

The Zephyr PR:https://github.com/zephyrproject-rtos/zephyr/pull/45294
also fixes this issue.

BRANCH=none
BUG=b:231667217
TEST=pass "make buildall -j4"
TEST=Test on Volteer, make sure the platform bootup to ChromeOS.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: If929fe48246e0902b182143031f99af019fca1f0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3626850
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>

4 files changed, 34 insertions, 0 deletions

diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h
index 434c3a7889..8404f16635 100644
--- a/chip/npcx/config_chip-npcx7.h
+++ b/chip/npcx/config_chip-npcx7.h
@@ -52,6 +52,15 @@
 
 /* 64-bit timer support */
 #define NPCX_ITIM64_SUPPORT
+
+/*
+ * Workaound the issue 3.10 in the NPCX99nF errata rev1.2
+ * Enabling an eSPI channel (e.g. Peripheral Channel, Virtual Wire Channel, etc.
+ * ) during an eSPI transaction might (with low probability) cause the eSPI_SIF
+ * module to transition to a wrong state and therefore response with FATAL_ERROR
+ * on an incoming transaction.
+ */
+#define NPCX_ESPI_BYPASS_CH_ENABLE_FATAL_ERROR
 #else
 #define UART_MODULE_COUNT 1
 #endif
diff --git a/chip/npcx/config_chip-npcx9.h b/chip/npcx/config_chip-npcx9.h
index 8844392ed9..7f154dbe42 100644
--- a/chip/npcx/config_chip-npcx9.h
+++ b/chip/npcx/config_chip-npcx9.h
@@ -60,6 +60,15 @@
 #define NPCX_PSL_CFG_PSL_OUT_OD		BIT(1)
 #define CONFIG_HIBERNATE_PSL_OUT_FLAGS	0
 
+/*
+ * Workaound the issue 3.10 in the NPCX99nF errata rev1.2
+ * Enabling an eSPI channel (e.g. Peripheral Channel, Virtual Wire Channel, etc.
+ * ) during an eSPI transaction might (with low probability) cause the eSPI_SIF
+ * module to transition to a wrong state and therefore response with FATAL_ERROR
+ * on an incoming transaction.
+ */
+#define NPCX_ESPI_BYPASS_CH_ENABLE_FATAL_ERROR
+
 /*****************************************************************************/
 /* Memory mapping */
 
diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c
index 6541ddeaae..d7d5f2c79d 100644
--- a/chip/npcx/espi.c
+++ b/chip/npcx/espi.c
@@ -623,6 +623,15 @@ void espi_init(void)
 {
 	int i;
 
+	if (IS_ENABLED(NPCX_ESPI_BYPASS_CH_ENABLE_FATAL_ERROR)) {
+		/* Enable the access to the NPCX_ONLY_ESPI_REG2 register */
+		NPCX_ONLY_ESPI_REG1 = NPCX_ONLY_ESPI_REG1_UNLOCK_REG2;
+		CLEAR_BIT(NPCX_ONLY_ESPI_REG2,
+			  NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG);
+		/* Disable the access to the NPCX_ONLY_ESPI_REG2 register */
+		NPCX_ONLY_ESPI_REG1 = NPCX_ONLY_ESPI_REG1_LOCK_REG2;
+	}
+
 	/* Support all channels */
 	NPCX_ESPICFG |= ESPI_SUPP_CH_ALL;
 
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h
index 5a140e60b8..8f0c7431a6 100644
--- a/chip/npcx/registers.h
+++ b/chip/npcx/registers.h
@@ -1111,6 +1111,13 @@ enum PM_CHANNEL_T {
 #define NPCX_FLASHCTL               REG32(NPCX_ESPI_BASE_ADDR + 0X38)
 #define NPCX_ESPIERR                REG32(NPCX_ESPI_BASE_ADDR + 0X3C)
 
+#define NPCX_ONLY_ESPI_REG1         REG8(NPCX_ESPI_BASE_ADDR + 0XF0)
+#define NPCX_ONLY_ESPI_REG2         REG8(NPCX_ESPI_BASE_ADDR + 0XF1)
+
+#define NPCX_ONLY_ESPI_REG1_UNLOCK_REG2         0x55
+#define NPCX_ONLY_ESPI_REG1_LOCK_REG2           0
+#define NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG    4
+
 /* eSPI Virtual Wire channel registers */
 #define NPCX_VWEVSM(n)              REG32(NPCX_ESPI_BASE_ADDR + 0x100 + (4*(n)))
 #define NPCX_VWEVMS(n)              REG32(NPCX_ESPI_BASE_ADDR + 0x140 + (4*(n)))