chip: Remove -march, since -mcpu itself is sufficient

According to the GCC documentation:

-mcpu specifies the name of the target ARM processor. GCC uses this name
to derive the name of the target ARM architecture (as if specified by
-march) and the ARM processor type for which to tune for performance (as
if specified by -mtune).

https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html

This means that unless we're overriding some setting with -march or
-mtune, there's no need to specify them. In our case, we aren't
overriding the default for -mtune that -mcpu sets, so make things
simpler by only specifying -mcpu.

Additional details in
https://community.arm.com/arm-community-blogs/b/tools-software-ides-blog/posts/compiler-flags-across-architectures-march-mtune-and-mcpu

BRANCH=none
BUG=b:145677491
TEST=./util/compare_build.sh -b all -j 120
     => MATCH

Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I1999ef25642ed9e32b2e8eeb76d4ba7a23dc2b8a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3699792
Reviewed-by: Andrea Grandi <agrandi@google.com>

6 files changed, 10 insertions, 15 deletions

diff --git a/chip/max32660/build.mk b/chip/max32660/build.mk
index e0f5636b2e..67fa079ca3 100644
--- a/chip/max32660/build.mk
+++ b/chip/max32660/build.mk
@@ -9,7 +9,7 @@
 # MAX32660 SoC has a Cortex-M4F ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 
 # Required chip modules
 chip-y=clock_chip.o gpio_chip.o system_chip.o hwtimer_chip.o uart_chip.o
diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk
index 6dec772ce3..1e3de24d06 100644
--- a/chip/mchp/build.mk
+++ b/chip/mchp/build.mk
@@ -15,7 +15,7 @@ endif
 # MCHP MEC SoC's have a Cortex-M4 ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 
 # JTAG debug with Keil ARM MDK debugger
 # do not allow GCC dwarf debug extensions
diff --git a/chip/mec1322/build.mk b/chip/mec1322/build.mk
index a17a2cad5f..7dadf60c88 100644
--- a/chip/mec1322/build.mk
+++ b/chip/mec1322/build.mk
@@ -9,7 +9,7 @@
 # MEC1322 SoC has a Cortex-M4 ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 
 ifeq ($(CONFIG_LTO),y)
 # Re-include the core's build.mk file so we can remove the lto flag.
diff --git a/chip/mt_scp/mt818x/build.mk b/chip/mt_scp/mt818x/build.mk
index bf450fb135..e9f77a2833 100644
--- a/chip/mt_scp/mt818x/build.mk
+++ b/chip/mt_scp/mt818x/build.mk
@@ -4,7 +4,7 @@
 # found in the LICENSE file.
 
 CORE:=cortex-m
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 
 # Required chip modules
 chip-y+=mt818x/clock_$(CHIP_VARIANT).o
diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk
index 1fe524763b..d7e61de4de 100644
--- a/chip/npcx/build.mk
+++ b/chip/npcx/build.mk
@@ -9,7 +9,7 @@
 # NPCX SoC has a Cortex-M4F ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 
 # Disable overlapping section warning that linker emits due to NPCX_RO_HEADER.
 LDFLAGS_EXTRA+=-Wl,--no-check-sections
diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk
index 13a6aa752a..5b2d7d9994 100644
--- a/chip/stm32/build.mk
+++ b/chip/stm32/build.mk
@@ -9,33 +9,28 @@
 ifeq ($(CHIP_FAMILY),stm32f0)
 # STM32F0xx sub-family has a Cortex-M0 ARM core
 CORE:=cortex-m0
-# Force ARMv6-M ISA used by the Cortex-M0
-# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M
-# without "svc" instruction, but that was short-lived. ARMv6S-M was the option
-# with "svc". GCC kept that naming scheme even though the distinction is long
-# gone.
-CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0
+CFLAGS_CPU+=-mcpu=cortex-m0
 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f3 stm32l4 stm32f4 \
 stm32g4))
 # STM32F3xx and STM32L4xx sub-family has a Cortex-M4 ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32h7))
 # STM32FH7xx family has a Cortex-M7 ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set (identical to M7)
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32l5))
 # STM32FL5xx family has a Cortex-M33 ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M33 instruction set
-CFLAGS_CPU+=-march=armv8-m.main+dsp -mcpu=cortex-m33
+CFLAGS_CPU+=-mcpu=cortex-m33
 else
 # other STM32 SoCs have a Cortex-M3 ARM core
 CORE:=cortex-m
 # Force Cortex-M3 subset of instructions
-CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3
+CFLAGS_CPU+=-mcpu=cortex-m3
 endif
 
 # Select between 16-bit and 32-bit timer for clock source