diff options
| author | Li Feng <li1.feng@intel.com> | 2022-05-20 21:08:04 -0700 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-06-14 00:45:40 +0000 |
| commit | df5ff1c3dc03c818d294fffdb4fd549c75cd5e41 (patch) | |
| tree | 6db7fef1a28db50873547dd84451e75b10aa8c7e | |
| parent | 5e7e791268ed81059d6919ad98721ec0db80c3ab (diff) | |
| download | chrome-ec-df5ff1c3dc03c818d294fffdb4fd549c75cd5e41.tar.gz | |
zephyr: MTL driving PCH_PWROK from EC
Porting from CL:3585883.
BUG=none
BRANCH=none
TEST=MTL-RVP can boot to S0
Signed-off-by: Li Feng <li1.feng@intel.com>
Change-Id: I4fa2be2560f9eb31908a5676fec97a8912568542
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3658302
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Andrew McRae <amcrae@google.com>
| -rw-r--r-- | zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts | 9 | ||||
| -rw-r--r-- | zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c | 33 |
2 files changed, 27 insertions, 15 deletions
diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts index 81219636f0..57b41bd9d2 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts @@ -43,11 +43,18 @@ gpios = <&gpioa 1 GPIO_ACTIVE_LOW>; interrupt-flags = <GPIO_INT_EDGE_BOTH>; }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpiod 3 GPIO_OPEN_DRAIN>; + output; + }; pwr-ec-pch-sys-pwrok { compatible = "intel,ap-pwrseq-gpio"; dbg-label = "SYS_PWROK output to PCH"; enum-name = "PWR_EC_PCH_SYS_PWROK"; - gpios = <&gpiof 5 0>; + gpios = <&gpiof 5 GPIO_OPEN_DRAIN>; output; }; pwr-sys-rst-l { diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c index d6430e906c..5183824117 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c @@ -9,27 +9,32 @@ LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL); static void ap_off(void) { + power_signal_set(PWR_PCH_PWROK, 0); power_signal_set(PWR_EC_PCH_SYS_PWROK, 0); } /* Generate SYS_PWROK->SOC if needed by system */ -static void generate_sys_pwrok_handler(void) +static void generate_pwrok_handler(void) { + int all_sys_pwrgd_in; + if (power_signal_get(PWR_EC_PCH_SYS_PWROK) == 0) { k_msleep(AP_PWRSEQ_DT_VALUE(sys_pwrok_delay)); - /* - * Loop through all PWROK signals defined by the board and set - * to match the current ALL_SYS_PWRGD input. - */ - if (power_signal_get(PWR_ALL_SYS_PWRGD) == 0) { - LOG_DBG("PG_EC_ALL_SYS_PWRGD deasserted, " - "shutting AP off!"); - ap_off(); - return; - } - LOG_INF("Turning on PWR_EC_PCH_SYS_PWROK"); - power_signal_set(PWR_EC_PCH_SYS_PWROK, 1); } + + all_sys_pwrgd_in = power_signal_get(PWR_ALL_SYS_PWRGD); + /* Loop through all PWROK signals defined by the board */ + if (all_sys_pwrgd_in == 0) { + LOG_DBG("PG_EC_ALL_SYS_PWRGD deasserted, " + "shutting AP off!"); + ap_off(); + return; + } + + power_signal_set(PWR_EC_PCH_SYS_PWROK, all_sys_pwrgd_in); + /* PCH_PWROK is set to combined result of ALL_SYS_PWRGD and SLP_S3 */ + power_signal_set(PWR_PCH_PWROK, all_sys_pwrgd_in && + !power_signal_get(PWR_SLP_S3)); } /* Chipset specific power state machine handler */ @@ -45,7 +50,7 @@ enum power_states_ndsx chipset_pwr_sm_run(enum power_states_ndsx curr_state) break; case SYS_POWER_STATE_S0: /* Send SYS_PWROK->SoC if conditions met */ - generate_sys_pwrok_handler(); + generate_pwrok_handler(); break; default: break; |