diff options
| author | Scott Collyer <scollyer@google.com> | 2020-07-30 22:06:56 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-08-13 10:37:35 +0000 |
| commit | dcbec910dc3ee7896ac03ce242007749057361be (patch) | |
| tree | fb212cad7c94f064ef9f5856469a1685144e1bad | |
| parent | c920804920510cb32961922508e3e46d65d0a980 (diff) | |
| download | chrome-ec-dcbec910dc3ee7896ac03ce242007749057361be.tar.gz | |
stm32g4: Fix max clock freq and flash wait state
The clock frequency macro added in previous CL was missing the
'0'. This CL fixes that error and makes a minor change to how the
flash wait state value is configured. Previously, setting of the wait
state field was disabling instruction/data cache until it was restored
in the next instruction. This results in swd debugger not remaining
attached.
BUG=b:148493929
BRANCH=None
TEST=verified console is working and debugger remains attached after
setting wait state to the correct value.
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I65e3a22e36de0bbf14926e5687a995b7e5717e7f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2340695
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
| -rw-r--r-- | chip/stm32/clock-stm32g4.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/chip/stm32/clock-stm32g4.c b/chip/stm32/clock-stm32g4.c index 4a91e1ad42..172a68ce66 100644 --- a/chip/stm32/clock-stm32g4.c +++ b/chip/stm32/clock-stm32g4.c @@ -24,9 +24,9 @@ #define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) #define MHZ(x) ((x) * 1000000) -#define WAIT_STATE_FREQ_STEP_HZ MHZ(2) +#define WAIT_STATE_FREQ_STEP_HZ MHZ(20) /* PLL configuration constants */ -#define STM32G4_SYSCLK_MAX_HZ MHZ(17) +#define STM32G4_SYSCLK_MAX_HZ MHZ(170) #define STM32G4_HSI_CLK_HZ MHZ(16) #define STM32G4_PLL_IN_FREQ_HZ MHZ(4) #define STM32G4_PLL_R 2 @@ -152,6 +152,7 @@ static void stm32g4_config_high_speed_clock(uint32_t hclk_hz, void stm32g4_set_flash_ws(uint32_t freq_hz) { + int ws; ASSERT(freq_hz <= STM32G4_SYSCLK_MAX_HZ); /* @@ -160,11 +161,10 @@ void stm32g4_set_flash_ws(uint32_t freq_hz) * found in Table 9 of RM0440 - STM32G4 technical reference manual. A * table lookup is not required though as WS = HCLK (MHz) / 20 */ - STM32_FLASH_ACR = (freq_hz / WAIT_STATE_FREQ_STEP_HZ) | - STM32_FLASH_ACR_PRFTEN; + ws = freq_hz / WAIT_STATE_FREQ_STEP_HZ; /* Enable data and instruction cache */ STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN | - STM32_FLASH_ACR_PRFTEN; + STM32_FLASH_ACR_PRFTEN | ws; } void clock_init(void) |