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| author | Ting Shen <phoenixshen@google.com> | 2022-07-04 16:27:39 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-07-07 08:38:56 +0000 |
| commit | f13bdb1b0ccab042f11db99d2f1a3b7599684a5a (patch) | |
| tree | f249320bc877588260b849b614a3ec234d3fbd55 | |
| parent | c39eac58cfc60e6937eadc4dca1dbdd1762e6410 (diff) | |
| download | chrome-ec-f13bdb1b0ccab042f11db99d2f1a3b7599684a5a.tar.gz | |
zephyr/it8xxx2: increase the image size to 1MB
Set CONFIG_FLASH_SIZE_BYTES back to 1MB to match the hard-coded number
in tast.
After this CL, the region mapping become:
384kB RO + PSTATE
384kB RW
256kB unused
This CL doesn't increase the RO/RW region size, only adds a 256kB
unallocated region at the end of FLASH. So the performance of
software sync should be the same.
BUG=b:237350549
TEST=1) size of zephyr.bin is still 768kB
2) `dut-control ec_flash_size` prints 1MB instead of 768kB
3) ec software sync and sysjump works
4) fw region macros doesn't change:
CONFIG_FW_PSTATE_SIZE: 4096
CONFIG_FW_PSTATE_OFF: 389120
CONFIG_RO_MEM_OFF: 0
CONFIG_RO_STORAGE_OFF: 0
CONFIG_RO_SIZE: 393216
CONFIG_RW_MEM_OFF: 393216
CONFIG_RW_STORAGE_OFF: 0
CONFIG_RW_SIZE: 393216
CONFIG_EC_PROTECTED_STORAGE_OFF: 0
CONFIG_EC_PROTECTED_STORAGE_SIZE: 393216
CONFIG_EC_WRITABLE_STORAGE_OFF: 393216
CONFIG_EC_WRITABLE_STORAGE_SIZE: 393216
CONFIG_WP_STORAGE_OFF: 0
CONFIG_WP_STORAGE_SIZE: 393216
BRANCH=none
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I598186737cfef4db50c4eecfc846800e17dfd537
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3742961
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Reviewed-by: Dino Li <dino.li@ite.corp-partner.google.com>
| -rw-r--r-- | zephyr/shim/chip/it8xxx2/include/flash_chip.h | 2 | ||||
| -rw-r--r-- | zephyr/shim/include/config_chip.h | 8 |
2 files changed, 1 insertions, 9 deletions
diff --git a/zephyr/shim/chip/it8xxx2/include/flash_chip.h b/zephyr/shim/chip/it8xxx2/include/flash_chip.h index ce8cc326ff..06b33ee6e1 100644 --- a/zephyr/shim/chip/it8xxx2/include/flash_chip.h +++ b/zephyr/shim/chip/it8xxx2/include/flash_chip.h @@ -28,6 +28,6 @@ */ #define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE #define CONFIG_FW_PSTATE_OFF \ - (CONFIG_FLASH_SIZE_BYTES / 2 - CONFIG_FW_PSTATE_SIZE) + (CONFIG_RO_STORAGE_OFF + CONFIG_RO_SIZE - CONFIG_FW_PSTATE_SIZE) #endif /* __CROS_EC_FLASH_CHIP_H */ diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h index 05a927796f..102238be83 100644 --- a/zephyr/shim/include/config_chip.h +++ b/zephyr/shim/include/config_chip.h @@ -562,15 +562,7 @@ extern struct jump_data mock_jump_data; #undef CONFIG_FLASH_SIZE_BYTES #ifdef CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES -/* - * Flash size of IT81202 is 1MB. - * We use only 3/4 space of flash to save time of erasing RW image from flash. - */ -#ifdef CONFIG_SOC_IT8XXX2 -#define CONFIG_FLASH_SIZE_BYTES (CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES * 3 / 4) -#else #define CONFIG_FLASH_SIZE_BYTES CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES -#endif #endif /* CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES */ #undef CONFIG_ADC |