diff options
| author | Ruibin Chang <ruibin.chang@ite.com.tw> | 2020-08-14 10:32:00 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-08-17 06:09:48 +0000 |
| commit | 7452789e6e47a5b357dc5270b07b17fd35008926 (patch) | |
| tree | ce904f7309da722bce5611fbf6214fb4a960a1e7 | |
| parent | 5b4724508d35eee1d45fa748a5ad05e914087bf7 (diff) | |
| download | chrome-ec-7452789e6e47a5b357dc5270b07b17fd35008926.tar.gz | |
Clean up: set embedded flash clock 48MHz as default
For chip it8xxx2 series and it8320dx, we set embedded flash clock
48MHz as default.
BUG=none
BRANCH=none
TEST=build all
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I100d70fbf80430ae98fa14c557886c4a37d8b93a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355164
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
| -rw-r--r-- | baseboard/dedede/baseboard.h | 3 | ||||
| -rw-r--r-- | baseboard/octopus/baseboard.h | 3 | ||||
| -rw-r--r-- | board/it8xxx2_pdevb/board.h | 3 | ||||
| -rw-r--r-- | board/reef_it8320/board.h | 1 | ||||
| -rw-r--r-- | chip/it83xx/config_chip_it8320.h | 1 | ||||
| -rw-r--r-- | chip/it83xx/config_chip_it8xxx2.h | 1 |
6 files changed, 2 insertions, 10 deletions
diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h index d6257ba903..ce2aafd76c 100644 --- a/baseboard/dedede/baseboard.h +++ b/baseboard/dedede/baseboard.h @@ -33,9 +33,6 @@ #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ #elif defined(VARIANT_DEDEDE_EC_IT8320) - /* Flash clock must be > (50Mhz / 2) */ - #define CONFIG_IT83XX_FLASH_CLOCK_48MHZ - #define I2C_PORT_EEPROM IT83XX_I2C_CH_A #define I2C_PORT_BATTERY IT83XX_I2C_CH_B #define I2C_PORT_SENSOR IT83XX_I2C_CH_C diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h index dae0794fae..c8e4b24e56 100644 --- a/baseboard/octopus/baseboard.h +++ b/baseboard/octopus/baseboard.h @@ -58,9 +58,6 @@ /* Allow the EC to enter deep sleep in S0 */ #define CONFIG_LOW_POWER_S0 #elif defined(VARIANT_OCTOPUS_EC_ITE8320) - /* Flash clock must be > (50Mhz / 2) */ - #define CONFIG_IT83XX_FLASH_CLOCK_48MHZ - /* I2C Bus Configuration */ #define I2C_PORT_BATTERY IT83XX_I2C_CH_A /* Shared bus */ #define I2C_PORT_CHARGER IT83XX_I2C_CH_A /* Shared bus */ diff --git a/board/it8xxx2_pdevb/board.h b/board/it8xxx2_pdevb/board.h index 79062b5594..491691cc44 100644 --- a/board/it8xxx2_pdevb/board.h +++ b/board/it8xxx2_pdevb/board.h @@ -36,9 +36,6 @@ #undef CONFIG_CMD_MMAPINFO #undef CONFIG_SWITCH -/* EC */ -#define CONFIG_IT83XX_FLASH_CLOCK_48MHZ - /* PD */ #define CONFIG_USB_PD_ALT_MODE #define CONFIG_USB_PD_ALT_MODE_DFP diff --git a/board/reef_it8320/board.h b/board/reef_it8320/board.h index 22b6e750d1..fb26e2ff57 100644 --- a/board/reef_it8320/board.h +++ b/board/reef_it8320/board.h @@ -142,7 +142,6 @@ #define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER #define CONFIG_PWR_STATE_DISCHARGE_FULL #undef CONFIG_KEYBOARD_VIVALDI -#define CONFIG_IT83XX_FLASH_CLOCK_48MHZ /* * Enable 1 slot of secure temporary storage to support diff --git a/chip/it83xx/config_chip_it8320.h b/chip/it83xx/config_chip_it8320.h index 7fc191f11c..6163ef8fb9 100644 --- a/chip/it83xx/config_chip_it8320.h +++ b/chip/it83xx/config_chip_it8320.h @@ -54,6 +54,7 @@ #define IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES #elif defined(CHIP_VARIANT_IT8320DX) #define CONFIG_FLASH_SIZE 0x00080000 +#define CONFIG_IT83XX_FLASH_CLOCK_48MHZ /* * Disable eSPI pad, then PLL change * (include EC clock frequency) is succeed even CS# is low. diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index dbcd6b9dd9..fd7d4e94dd 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -14,6 +14,7 @@ #define CHIP_ILM_DLM_ORDER /* The base address of EC interrupt controller registers. */ #define CHIP_EC_INTC_BASE 0x00F03F00 +#define CONFIG_IT83XX_FLASH_CLOCK_48MHZ /* * ILM/DLM size register. * bit[3-0] ILM size: |