diff options
| author | poornima tom <poornima.tom@intel.com> | 2022-03-23 02:42:49 +0530 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-08-03 22:04:41 +0000 |
| commit | c3ab32c8973f1af547a0a118a0f11de21e4c029e (patch) | |
| tree | 701d7dc0105b0474316daafb85b2eb5edee666a4 | |
| parent | 1404036c889324442a9559812f5c4ed6143506f3 (diff) | |
| download | chrome-ec-c3ab32c8973f1af547a0a118a0f11de21e4c029e.tar.gz | |
ec_memmap: Add Power source to EC MEMMAP region
For Intel Dynamic Tuning Platform Power Participant,
power source(PSRC) is one of the object. This PSRC
corresponds to an 8 bit value, representing the current
power source as lower nibble and PD sequence number as
upper nibble. PSRC information must be updated at EC
and must be read by AP. As there is only a read request
from AP, this component could be present in EC_MEMMAP
region. Document #doc-626708, has more details.
BUG=b:205928013
BRANCH=None
TEST=make build_cros_ec_commands
Signed-off-by: poornima tom <poornima.tom@intel.com>
Change-Id: Iebfb305e95e647cbe3d83a351765b7711070981e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3545778
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | include/ec_commands.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/ec_commands.h b/include/ec_commands.h index 68446d0f38..27a3ca1bd5 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -168,9 +168,9 @@ extern "C" { /* 0x92: Lid Angle if available, LID_ANGLE_UNRELIABLE otherwise */ /* 0x94 - 0x99: 1st Accelerometer */ /* 0x9a - 0x9f: 2nd Accelerometer */ + #define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ #define EC_MEMMAP_GPU 0xa6 /* GPU-specific, 8 bits */ -/* Unused 0xa7 - 0xdf */ /* * Bit fields for EC_MEMMAP_GPU @@ -180,6 +180,10 @@ extern "C" { #define EC_MEMMAP_GPU_D_NOTIFY_MASK GENMASK(2, 0) #define EC_MEMMAP_GPU_OVERT_BIT BIT(3) +/* Power Participant related components */ +#define EC_MEMMAP_PWR_SRC 0xa7 /* Power source (8-bit) */ +/* Unused 0xa8 - 0xdf */ + /* * ACPI is unable to access memory mapped data at or above this offset due to * limitations of the ACPI protocol. Do not place data in the range 0xe0 - 0xfe |