rex: Add support for power sequencing

This CL adds the config options, power signals nodes, and
support functions required to support power sequencing.

BRANCH=none
BUG=b:240434243
TEST=zmake build rex

Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I932995ddac4831bc0be3efefd7d345beef122178
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3798471
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Fabio Baltieri <fabiobaltieri@google.com>
Commit-Queue: Scott Collyer <scollyer@chromium.org>

5 files changed, 226 insertions, 2 deletions

diff --git a/zephyr/projects/rex/BUILD.py b/zephyr/projects/rex/BUILD.py
index 97e90e69b6..10abc7d3be 100644
--- a/zephyr/projects/rex/BUILD.py
+++ b/zephyr/projects/rex/BUILD.py
@@ -32,6 +32,7 @@ register_variant(
     extra_dts_overlays=[
         here / "generated.dts",
         here / "interrupts.dts",
+        here / "power_signals.dts",
     ],
     extra_kconfig_files=[here / "prj_rex.conf"],
 )
diff --git a/zephyr/projects/rex/CMakeLists.txt b/zephyr/projects/rex/CMakeLists.txt
index 8a0349bb24..b724145961 100644
--- a/zephyr/projects/rex/CMakeLists.txt
+++ b/zephyr/projects/rex/CMakeLists.txt
@@ -4,6 +4,8 @@
 
 cmake_minimum_required(VERSION 3.20.5)
 find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(ec)
+project(rex)
 
 zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ "src/board_power.c")
+
diff --git a/zephyr/projects/rex/power_signals.dts b/zephyr/projects/rex/power_signals.dts
new file mode 100644
index 0000000000..1df4a4bb0c
--- /dev/null
+++ b/zephyr/projects/rex/power_signals.dts
@@ -0,0 +1,145 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <3>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP1800_S5/PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpiob 6 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpioe 2 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioa 6 0>;
+		output;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpioa 5 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpiob 0 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+		gpios = <&gpiof 4 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the corresponding named-gpios need to have no-auto-init set.
+ */
+ /* pwr-en-pp3300-s5 */
+&gpio_en_s5_rails {
+	no-auto-init;
+};
+
+/* pwr-pg-ec-rsmrst-od */
+&gpio_seq_ec_rsmrst_odl{
+	no-auto-init;
+};
+
+/* pwr-ec-pch-rsmrst-odl */
+&gpio_ec_soc_rsmrst_l{
+	no-auto-init;
+};
+
+/* pwr-pch-pwrok */
+&gpio_soc_pwrok{
+	no-auto-init;
+};
+
+/* pwr-ec-pch-sys-pwrok */
+&gpio_sys_pwrok{
+	no-auto-init;
+};
+
+/* pwr-sys-rst-l */
+&gpio_sys_rst_odl{
+	no-auto-init;
+};
+
+/* pwr-slp-s0-l */
+&gpio_sys_slp_s0ix_3v3_l{
+	no-auto-init;
+};
+
+/* pwr-slp-s3-l */
+&gpio_slp_s3_ls_l{
+	no-auto-init;
+};
+
+/* pwr-all-sys-pwrgd */
+&gpio_seq_ec_all_sys_pg{
+	no-auto-init;
+};
+
diff --git a/zephyr/projects/rex/prj.conf b/zephyr/projects/rex/prj.conf
index 3dfb636b9e..f7f00a82d3 100644
--- a/zephyr/projects/rex/prj.conf
+++ b/zephyr/projects/rex/prj.conf
@@ -22,9 +22,9 @@ CONFIG_PLATFORM_EC_VBOOT_EFS2=n
 
 # Application processor; communicates with EC via eSPI
 CONFIG_AP=y
-CONFIG_AP_X86_INTEL_MTL=y
 CONFIG_ESPI=y
 CONFIG_ESPI_LOG_LEVEL_ERR=y
+CONFIG_PLATFORM_EC_ESPI_VW_SLP_S3=y
 CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4=y
 CONFIG_PLATFORM_EC_ESPI_VW_SLP_S5=y
 CONFIG_PLATFORM_EC_HOSTCMD=y
@@ -32,6 +32,21 @@ CONFIG_PLATFORM_EC_HOSTCMD=y
 CONFIG_PLATFORM_EC_THROTTLE_AP=n
 CONFIG_PLATFORM_EC_PORT80=y
 
+# Power Sequecing
+CONFIG_AP_X86_INTEL_MTL=y
+CONFIG_X86_NON_DSX_PWRSEQ_MTL=y
+CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD=y
+# TODO (b/240434243): This may be needed, but using eSPI VW for now
+CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE=n
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+# Note: this config will prevent AP from powering on automatically
+CONFIG_PLATFORM_EC_BRINGUP=y
+
+# Zephyr Inbuilt AP Power Sequencing Config
+CONFIG_AP_PWRSEQ=y
+CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE=y
+CONFIG_AP_PWRSEQ_S0IX=y
+
 # ADC
 CONFIG_ADC=y
 
diff --git a/zephyr/projects/rex/src/board_power.c b/zephyr/projects/rex/src/board_power.c
new file mode 100644
index 0000000000..922d2f8324
--- /dev/null
+++ b/zephyr/projects/rex/src/board_power.c
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/gpio.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_events.h>
+#include <ap_power/ap_power_interface.h>
+#include <ap_power_override_functions.h>
+#include <power_signals.h>
+#include <x86_power_signals.h>
+
+#include "gpio_signal.h"
+#include "gpio/gpio.h"
+
+LOG_MODULE_DECLARE(ap_pwrseq, LOG_LEVEL_INF);
+
+#if CONFIG_X86_NON_DSX_PWRSEQ_MTL
+#define X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS 50
+
+void board_ap_power_force_shutdown(void)
+{
+	int timeout_ms = X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS;
+
+	/* Turn off PCH_RMSRST to meet tPCH12 */
+	power_signal_set(PWR_EC_PCH_RSMRST, 0);
+
+	/* Turn off PRIM load switch. */
+	power_signal_set(PWR_EN_PP3300_A, 0);
+
+	/* Wait RSMRST to be off. */
+	while (power_signal_get(PWR_RSMRST) && (timeout_ms > 0)) {
+		k_msleep(1);
+		timeout_ms--;
+	};
+
+	if (power_signal_get(PWR_RSMRST)) {
+		LOG_WRN("RSMRST_ODL didn't go low!  Assuming G3.");
+	}
+}
+
+void board_ap_power_action_g3_s5(void)
+{
+	/* Turn on the PP3300_PRIM rail. */
+	power_signal_set(PWR_EN_PP3300_A, 1);
+
+	if (!power_wait_signals_timeout(
+		    IN_PGOOD_ALL_CORE,
+		    AP_PWRSEQ_DT_VALUE(wait_signal_timeout))) {
+		ap_power_ev_send_callbacks(AP_POWER_PRE_INIT);
+	}
+}
+
+bool board_ap_power_check_power_rails_enabled(void)
+{
+	return power_signal_get(PWR_EN_PP3300_A);
+}
+#endif /* CONFIG_X86_NON_DSX_PWRSEQ_MTL */