diff options
| author | Tinghan Shen <tinghan.shen@mediatek.com> | 2022-07-28 15:55:55 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-08-16 12:22:45 +0000 |
| commit | 2e68f3ee03f51fb0a3f8c0cad6868b2f1fb34a5a (patch) | |
| tree | 11d617a54c9411959e3a6d210c7d80ec89f62e39 | |
| parent | 1e8e8eca960b6914ff50d219d249558cdc9974be (diff) | |
| download | chrome-ec-2e68f3ee03f51fb0a3f8c0cad6868b2f1fb34a5a.tar.gz | |
chip/mt_scp: remove gpio configuration
The UART console is mainly for debug purpose. Remove it to
prevent malicious usage of this interface. If required, a user
can configure the pin mux by kernel dts.
Take mt8195 as an example to enable the SCP UART in dts,
scp_pins: scp {
pins_scp_vreq {
pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>;
bias-disable;
input-enable;
};
+
+ pins_uart {
+ pinmux = <PINMUX_GPIO102__FUNC_TP_UTXD1_AO>,
+ <PINMUX_GPIO103__FUNC_TP_URXD1_AO>;
+ bias-pull-up;
+ };
};
BUG=none
TEST=boot cherry scp ok.
scp boot log still records in /var/log/cros_scp.log
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Change-Id: I37bc65b47e7423e9def5a399ba7ceb2761dc9615
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3791283
Tested-by: TingHan Shen <tinghan.shen@mediatek.corp-partner.google.com>
Reviewed-by: Wei-Shun Chang <weishunc@chromium.org>
Commit-Queue: Wei-Shun Chang <weishunc@chromium.org>
| -rw-r--r-- | chip/mt_scp/mt818x/uart.c | 1 | ||||
| -rw-r--r-- | chip/mt_scp/mt8192/uart.c | 4 | ||||
| -rw-r--r-- | chip/mt_scp/mt8195/uart.c | 4 |
3 files changed, 0 insertions, 9 deletions
diff --git a/chip/mt_scp/mt818x/uart.c b/chip/mt_scp/mt818x/uart.c index 4b3b45d8ea..e6bd361d8d 100644 --- a/chip/mt_scp/mt818x/uart.c +++ b/chip/mt_scp/mt818x/uart.c @@ -174,6 +174,5 @@ void uart_init(void) /* UART RX IRQ needs an extra enable */ SCP_INTC_UART_RX_IRQ |= 1 << UARTN; #endif - gpio_config_module(MODULE_UART, 1); uart_done = 1; } diff --git a/chip/mt_scp/mt8192/uart.c b/chip/mt_scp/mt8192/uart.c index 0ebb93cbb4..9e2c097414 100644 --- a/chip/mt_scp/mt8192/uart.c +++ b/chip/mt_scp/mt8192/uart.c @@ -19,10 +19,6 @@ void uart_init_pinmux(void) #if UARTN == 0 SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC); SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST; - - /* set AP GPIO164 and GPIO165 to alt func 3 */ - AP_GPIO_MODE20_CLR = 0x00770000; - AP_GPIO_MODE20_SET = 0x00330000; #elif UARTN == 1 SCP_UART_CK_SEL |= UART1_CK_SEL_VAL(UART_CK_SEL_ULPOSC); SCP_SET_CLK_CG |= CG_UART1_MCLK | CG_UART1_BCLK | CG_UART1_RST; diff --git a/chip/mt_scp/mt8195/uart.c b/chip/mt_scp/mt8195/uart.c index 76674fa7d3..dab25e7d19 100644 --- a/chip/mt_scp/mt8195/uart.c +++ b/chip/mt_scp/mt8195/uart.c @@ -19,9 +19,5 @@ void uart_init_pinmux(void) #if UARTN == 0 SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC); SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST; - - /* set AP GPIO102 and GPIO103 to alt func 5 */ - AP_GPIO_MODE12_CLR = 0x77000000; - AP_GPIO_MODE12_SET = 0x55000000; #endif } |