diff options
| author | Scott Collyer <scollyer@google.com> | 2022-08-24 11:57:16 -0700 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-08-24 23:44:38 +0000 |
| commit | 01e90e3e76e5d11e214be6d2e4da11defc450638 (patch) | |
| tree | 2966a28045aa5c360ad7ddc7103ef8b5bbfc9bcd | |
| parent | 0db8acf994dd4a431c216c0a01bfaa5d08598c1b (diff) | |
| download | chrome-ec-01e90e3e76e5d11e214be6d2e4da11defc450638.tar.gz | |
rex: Make SOC_PWROK/SYS_PWROK signals TTL instead of OD
Both SOC_PWROK and SYS_PWROK signals are designed to be TTL outputs,
but they were being configured as open drain outputs in their power
signals node.
In addition, this CL adds an internal pullup to SEQ_EC_ALL_SYS_PG as
a work-around for the missing pullup on the board.
Lastly, for the gpio flags field, 0 was replaces with GPIO_ACTIVE_HIGH
for readability.
BRANCH=none
BUG=b:243638916
TEST=zmake build rex
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: Ifd7f88b863d5468fbcfa979d23b0071f429903d1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3855156
Tested-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Fabio Baltieri <fabiobaltieri@google.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
| -rw-r--r-- | zephyr/projects/rex/power_signals.dts | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/zephyr/projects/rex/power_signals.dts b/zephyr/projects/rex/power_signals.dts index bf96ead2af..a4cc3cb5ef 100644 --- a/zephyr/projects/rex/power_signals.dts +++ b/zephyr/projects/rex/power_signals.dts @@ -19,42 +19,42 @@ compatible = "intel,ap-pwrseq-gpio"; dbg-label = "PP1800_S5/PP3300_S5 enable output to LS"; enum-name = "PWR_EN_PP3300_A"; - gpios = <&gpiob 6 0>; + gpios = <&gpiob 6 GPIO_ACTIVE_HIGH>; output; }; pwr-pg-ec-rsmrst-od { compatible = "intel,ap-pwrseq-gpio"; dbg-label = "RSMRST power good from regulator"; enum-name = "PWR_RSMRST"; - gpios = <&gpioe 2 0>; + gpios = <&gpioe 2 GPIO_ACTIVE_HIGH>; interrupt-flags = <GPIO_INT_EDGE_BOTH>; }; pwr-ec-pch-rsmrst-odl { compatible = "intel,ap-pwrseq-gpio"; dbg-label = "RSMRST output to PCH"; enum-name = "PWR_EC_PCH_RSMRST"; - gpios = <&gpioa 6 0>; + gpios = <&gpioa 6 GPIO_ACTIVE_HIGH>; output; }; pwr-pch-pwrok { compatible = "intel,ap-pwrseq-gpio"; dbg-label = "PCH_PWROK output to PCH"; enum-name = "PWR_PCH_PWROK"; - gpios = <&gpioa 5 GPIO_OPEN_DRAIN>; + gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>; output; }; pwr-ec-pch-sys-pwrok { compatible = "intel,ap-pwrseq-gpio"; dbg-label = "SYS_PWROK output to PCH"; enum-name = "PWR_EC_PCH_SYS_PWROK"; - gpios = <&gpiob 0 GPIO_OPEN_DRAIN>; + gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>; output; }; pwr-sys-rst-l { compatible = "intel,ap-pwrseq-gpio"; dbg-label = "SYS_RESET# output to PCH"; enum-name = "PWR_SYS_RST"; - gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; output; }; pwr-slp-s0-l { @@ -96,7 +96,7 @@ compatible = "intel,ap-pwrseq-gpio"; dbg-label = "all power good"; enum-name = "PWR_ALL_SYS_PWRGD"; - gpios = <&gpiof 4 0>; + gpios = <&gpiof 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; interrupt-flags = <GPIO_INT_EDGE_BOTH>; }; }; |