zephyr: npcx: add hibernate callback implementation for cros_system.

This CL uses soc-specific functions for supporting hibernating.

It includes:
1. npcx_pinctrl_psl_input_configure() - Used to configure PSL input pads
from "psl-in-pads" property which detect the wake-up events. After ec
received them, PSL_OUT will be set to active level and the related
circuit will turn on core power supply (VCC1) from standby power state
(ultra-low-power mode) later.

2. npcx_pinctrl_psl_output_set_inactive() - Used to set PSL output pad
to inactive level. When PSL_OUT is in inactive level, VCC1 is turned off
for entering standby power state (ultra-low-power mode).

Use EC_SYSTEM_HIBERNATE_PSL to turn on this feature.

BUG=b:173787365
BRANCH=none
TEST=zmake testall, Press 'hibernate' on console and each
PSL input can wake-up ec from hibernating on volteer.

Cq-Depend: chromium:2793324
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I0fe3a9eb0c56e679c56bcb8abc1c6353ec46b5c9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2794206
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>

3 files changed, 46 insertions, 0 deletions

diff --git a/zephyr/Kconfig.system b/zephyr/Kconfig.system
index d8ae87b149..4fb681acc7 100644
--- a/zephyr/Kconfig.system
+++ b/zephyr/Kconfig.system
@@ -4,6 +4,14 @@
 
 if PLATFORM_EC
 
+config PLATFORM_EC_HIBERNATE_PSL
+	bool "System hibernating with PSL (Power Switch Logic) mechanism"
+	depends on SOC_FAMILY_NPCX
+	help
+	  Use PSL (Power Switch Logic) for hibernating. It turns off VCC power
+	  rail for ultra-low power consumption and uses PSL inputs rely on VSBY
+	  power rail to wake up ec and the whole system.
+
 config PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY
 	int "System pre-initialization priority"
 	default 20
diff --git a/zephyr/drivers/cros_system/cros_system_npcx.c b/zephyr/drivers/cros_system/cros_system_npcx.c
index 48e33188cf..67c2d799ac 100644
--- a/zephyr/drivers/cros_system/cros_system_npcx.c
+++ b/zephyr/drivers/cros_system/cros_system_npcx.c
@@ -115,6 +115,38 @@ static int cros_system_npcx_soc_reset(const struct device *dev)
 	return 0;
 }
 
+static int cros_system_npcx_hibernate(const struct device *dev,
+				      uint32_t seconds, uint32_t microseconds)
+{
+	ARG_UNUSED(seconds);
+	ARG_UNUSED(microseconds);
+
+	/* Disable interrupt first */
+	interrupt_disable_all();
+
+	/*
+	 * TODO(b:178230662): RTC wake-up in PSL mode only support in npcx9
+	 * series. Nuvoton will introduce CLs for it later.
+	 */
+
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_HIBERNATE_PSL)) {
+		/*
+		 * Configure PSL input pads from "psl-in-pads" property in
+		 * device tree file.
+		 */
+		npcx_pinctrl_psl_input_configure();
+
+		/* Turn off VCC1 and enter ultra-low-power mode */
+		npcx_pinctrl_psl_output_set_inactive();
+	}
+
+	/*
+	 * TODO(b:183745774): implement Non-PSL hibernate mechanism if
+	 * CONFIG_PLATFORM_EC_HIBERNATE_PSL is not enabled.
+	 */
+	return 0;
+}
+
 static struct cros_system_npcx_data cros_system_npcx_dev_data;
 
 static const struct cros_system_npcx_config cros_system_dev_cfg = {
@@ -125,6 +157,7 @@ static const struct cros_system_npcx_config cros_system_dev_cfg = {
 static const struct cros_system_driver_api cros_system_driver_npcx_api = {
 	.get_reset_cause = cros_system_npcx_get_reset_cause,
 	.soc_reset = cros_system_npcx_soc_reset,
+	.hibernate = cros_system_npcx_hibernate,
 };
 
 /*
diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h
index 626d9b6027..1f794fe2c6 100644
--- a/zephyr/shim/include/config_chip.h
+++ b/zephyr/shim/include/config_chip.h
@@ -1350,4 +1350,9 @@
 #define CONFIG_CHARGER_BQ25720
 #endif
 
+#undef CONFIG_HIBERNATE_PSL
+#ifdef CONFIG_PLATFORM_EC_HIBERNATE_PSL
+#define CONFIG_HIBERNATE_PSL
+#endif
+
 #endif  /* __CROS_EC_CONFIG_CHIP_H */