diff options
| author | Rob Barnes <robbarnes@google.com> | 2022-09-07 21:49:36 +0000 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-09-15 14:58:45 +0000 |
| commit | 9e271aa66ca3fa77c5c12352bc0b5c10ed827b8a (patch) | |
| tree | c4a104101f59a4bd8fcd9d0617b5ce377896b032 | |
| parent | 194340af091f7f474225d33324d75c81d675c180 (diff) | |
| download | chrome-ec-9e271aa66ca3fa77c5c12352bc0b5c10ed827b8a.tar.gz | |
zephyr/panic: Capture extra cortex-m registers
Copy callee saved registers to panic data structure.
Enable extra exception info by default.
Clang format affected lines.
BUG=b:245591465
BRANCH=none
TEST=Dump panic info on skyrim, observe extra registers
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I848d7e6bc35bf2b62b76182dd9d3fa87877a41fc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3880830
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
| -rw-r--r-- | zephyr/Kconfig.defaults | 3 | ||||
| -rw-r--r-- | zephyr/shim/src/panic.c | 40 |
2 files changed, 34 insertions, 9 deletions
diff --git a/zephyr/Kconfig.defaults b/zephyr/Kconfig.defaults index f7e1f710a2..ded7516748 100644 --- a/zephyr/Kconfig.defaults +++ b/zephyr/Kconfig.defaults @@ -31,4 +31,7 @@ config SHELL_THREAD_PRIORITY_OVERRIDE config SHELL_THREAD_PRIORITY default 12 # track EC_SHELL_PRIO +config EXTRA_EXCEPTION_INFO + default y if ARCH_HAS_EXTRA_EXCEPTION_INFO + orsource "Kconfig.defaults-$(ARCH)" diff --git a/zephyr/shim/src/panic.c b/zephyr/shim/src/panic.c index e27372be52..20f0e9977e 100644 --- a/zephyr/shim/src/panic.c +++ b/zephyr/shim/src/panic.c @@ -27,15 +27,37 @@ #if defined(CONFIG_ARM) #define PANIC_ARCH PANIC_ARCH_CORTEX_M -#define PANIC_REG_LIST(M) \ - M(basic.r0, cm.frame[0], a1) \ - M(basic.r1, cm.frame[1], a2) \ - M(basic.r2, cm.frame[2], a3) \ - M(basic.r3, cm.frame[3], a4) \ - M(basic.r12, cm.frame[4], ip) \ - M(basic.lr, cm.frame[5], lr) \ - M(basic.pc, cm.frame[6], pc) \ - M(basic.xpsr, cm.frame[7], xpsr) +#if defined(CONFIG_EXTRA_EXCEPTION_INFO) +#define EXTRA_PANIC_REG_LIST(M) \ + M(extra_info.callee->v1, cm.regs[CORTEX_PANIC_REGISTER_R4], v1) \ + M(extra_info.callee->v2, cm.regs[CORTEX_PANIC_REGISTER_R5], v2) \ + M(extra_info.callee->v3, cm.regs[CORTEX_PANIC_REGISTER_R6], v3) \ + M(extra_info.callee->v4, cm.regs[CORTEX_PANIC_REGISTER_R7], v4) \ + M(extra_info.callee->v5, cm.regs[CORTEX_PANIC_REGISTER_R8], v5) \ + M(extra_info.callee->v6, cm.regs[CORTEX_PANIC_REGISTER_R9], v6) \ + M(extra_info.callee->v7, cm.regs[CORTEX_PANIC_REGISTER_R10], v7) \ + M(extra_info.callee->v8, cm.regs[CORTEX_PANIC_REGISTER_R11], v8) \ + M(extra_info.callee->psp, cm.regs[CORTEX_PANIC_REGISTER_PSP], psp) \ + M(extra_info.exc_return, cm.regs[CORTEX_PANIC_REGISTER_LR], exc_rtn) \ + M(extra_info.msp, cm.regs[CORTEX_PANIC_REGISTER_MSP], msp) +/* + * IPSR is not copied. IPSR is a subset of xPSR, which is already + * captured in PANIC_REG_LIST. + */ +#else +#define EXTRA_PANIC_REG_LIST(M) +#endif +/* TODO(b/245423691): Copy other status registers (e.g. CFSR) when available. */ +#define PANIC_REG_LIST(M) \ + M(basic.r0, cm.frame[0], a1) \ + M(basic.r1, cm.frame[1], a2) \ + M(basic.r2, cm.frame[2], a3) \ + M(basic.r3, cm.frame[3], a4) \ + M(basic.r12, cm.frame[4], ip) \ + M(basic.lr, cm.frame[5], lr) \ + M(basic.pc, cm.frame[6], pc) \ + M(basic.xpsr, cm.frame[7], xpsr) \ + EXTRA_PANIC_REG_LIST(M) #define PANIC_REG_EXCEPTION(pdata) pdata->cm.regs[1] #define PANIC_REG_REASON(pdata) pdata->cm.regs[3] #define PANIC_REG_INFO(pdata) pdata->cm.regs[4] |