diff options
| author | Tom Hughes <tomhughes@chromium.org> | 2022-11-10 16:11:01 -0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-11-15 00:42:18 +0000 |
| commit | da42c4a3dbcbb51b228d2085a4b5896afbc57fd0 (patch) | |
| tree | c83acacac33ba9b37258f9887d1a6f64f868c96c | |
| parent | ded807b0e86401cdb9c054881a84142145e18f16 (diff) | |
| download | chrome-ec-da42c4a3dbcbb51b228d2085a4b5896afbc57fd0.tar.gz | |
core/cortex-m0: Use EC's builtins over compiler-rt
When examining code size, it appears that the builtins in compiler-rt
(especially for division) are larger than the ones in the EC source
code:
armv7m-cros-eabi-readelf -s ./build/servo_v4p1/RW/ec.RW.elf | sort -k3 -n -r
__udivsi3: 418 bytes
__aeabi_uidiv: 418 bytes
Compiling with clang before this change:
RO: 15560 bytes in flash and 864 bytes in RAM still available on servo_v4p1
RW: 848 bytes in flash and 7144 bytes in RAM still available on servo_v4p1
After this change:
RO: 16456 bytes in flash and 864 bytes in RAM still available on servo_v4p1
RW: 1232 bytes in flash and 7144 bytes in RAM still available on servo_v4p1
BRANCH=none
BUG=b:256193799
TEST=make buildall
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I21eab7fba10795e7821be79d141002a009d396a5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4021114
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
| -rw-r--r-- | core/cortex-m0/build.mk | 14 | ||||
| -rw-r--r-- | core/cortex-m0/config_core.h | 5 |
2 files changed, 12 insertions, 7 deletions
diff --git a/core/cortex-m0/build.mk b/core/cortex-m0/build.mk index 7de8956a4d..f3cce27eea 100644 --- a/core/cortex-m0/build.mk +++ b/core/cortex-m0/build.mk @@ -6,6 +6,14 @@ # Cortex-M0 core OS files build # +# When set to 1, exclusively use builtins from compiler-rt. +# When set to 0, use EC's builtins. +USE_LLVM_COMPILER_RT:=0 + +ifeq ($(USE_LLVM_COMPILER_RT),1) +CFLAGS_CPU+=-DUSE_LLVM_COMPILER_RT +endif + # CPU specific compilation flags CFLAGS_CPU+=-mthumb ifeq ($(cc-name),clang) @@ -24,14 +32,12 @@ LDFLAGS_EXTRA+=-flto endif core-y=cpu.o debug.o init.o thumb_case.o mula.o -# When using clang, we get these as builtins from compiler-rt. -ifneq ($(cc-name),clang) +ifeq ($(USE_LLVM_COMPILER_RT),0) core-y+=div.o lmul.o ldivmod.o uldivmod.o endif core-y+=vecttable.o -# When using clang, we get these as builtins from compiler-rt. -ifneq ($(cc-name),clang) +ifeq ($(USE_LLVM_COMPILER_RT),0) core-y+=__builtin.o endif core-$(CONFIG_COMMON_PANIC_OUTPUT)+=panic.o diff --git a/core/cortex-m0/config_core.h b/core/cortex-m0/config_core.h index 9ef52f848a..63e6da8972 100644 --- a/core/cortex-m0/config_core.h +++ b/core/cortex-m0/config_core.h @@ -12,12 +12,11 @@ /* * Emulate the CLZ/CTZ instructions since the CPU core is lacking support. - * When building with clang, we rely on compiler_rt to provide this support. */ -#ifndef __clang__ +#ifndef USE_LLVM_COMPILER_RT #define CONFIG_SOFTWARE_CLZ #define CONFIG_SOFTWARE_CTZ -#endif /* __clang__ */ +#endif /* USE_LLVM_COMPILER_RT */ #define CONFIG_ASSEMBLY_MULA32 |