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authorPatrick Georgi <pgeorgi@google.com>2016-02-01 18:46:35 +0100
committerchrome-bot <chrome-bot@chromium.org>2016-02-02 17:20:04 -0800
commit960cf45b3ffe88e842c27145e7e646d63a89c371 (patch)
tree6983741d1863ea6083961c0067c122f510550d9d
parentb7cf464b860839775412020541d8a09a8618210e (diff)
downloadchrome-ec-960cf45b3ffe88e842c27145e7e646d63a89c371.tar.gz
Don't declare functions inline that aren't always defined as such
gcc 5.2 bails out on an inline declaration that isn't followed up with a definition in the same compilation unit. BRANCH=none BUG=chrome-os-partner:49517 TEST=compile tested with coreboot's toolchain. samus, oak and others that failed now build. Change-Id: Ic9c28fc12c80e24ea0dbf85f35846fd6a0b56a2d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/324970 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
-rw-r--r--include/power.h4
-rw-r--r--include/task.h2
2 files changed, 3 insertions, 3 deletions
diff --git a/include/power.h b/include/power.h
index 5eff1f854a..64a1e7c4a5 100644
--- a/include/power.h
+++ b/include/power.h
@@ -124,14 +124,14 @@ int chipset_get_ps_debounced_level(enum gpio_signal signal);
*
* @return Whether we should pause in S5 when shutting down.
*/
-inline int power_get_pause_in_s5(void);
+int power_get_pause_in_s5(void);
/**
* pause_in_s5 setter method.
*
* @param pause True if we should pause in S5 when shutting down.
*/
-inline void power_set_pause_in_s5(int pause);
+void power_set_pause_in_s5(int pause);
#ifdef CONFIG_LOW_POWER_PSEUDO_G3
void enter_pseudo_g3(void);
diff --git a/include/task.h b/include/task.h
index ed635686bc..a1b133b986 100644
--- a/include/task.h
+++ b/include/task.h
@@ -49,7 +49,7 @@ void interrupt_enable(void);
/**
* Return true if we are in interrupt context.
*/
-inline int in_interrupt_context(void);
+int in_interrupt_context(void);
/**
* Return current interrupt mask. Meaning is chip-specific and