ucpd: Add support to turn off type-2 BIST mode

This CL adds changes to the ucpd driver to support turning off BIST
mode once it's been started. For ucpd, the peripheral has to be
disabled and reset for this purpose.

BUG=b:182436876
BRANCH=None
TEST=Verfied that honeybuns can pass TDA.2.1.1.1: BMC-PHY-TX-EYE
compliance test, which previously was failing because BIST type-2 mode
was not being stopped.

Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: Ib6aa898ef5727dd5887e5d1c0b2eee94fdb366b3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2751328
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>

2 files changed, 37 insertions, 6 deletions

diff --git a/chip/stm32/ucpd-stm32gx.c b/chip/stm32/ucpd-stm32gx.c
index e9693dfa1e..47045229fc 100644
--- a/chip/stm32/ucpd-stm32gx.c
+++ b/chip/stm32/ucpd-stm32gx.c
@@ -388,11 +388,23 @@ static void ucpd_rx_enque_error(void)
 }
 DECLARE_DEFERRED(ucpd_rx_enque_error);
 
+static void stm32gx_ucpd_state_init(int port)
+{
+	/* Init variables used to manage tx process */
+	ucpd_tx_request = 0;
+	tx_retry_count = 0;
+	ucpd_tx_state = STATE_IDLE;
+	ucpd_timeout_us = -1;
+}
+
 int stm32gx_ucpd_init(int port)
 {
 	uint32_t cfgr1_reg;
 	uint32_t moder_reg;
 
+	/* Disable UCPD interrupts */
+	task_disable_irq(STM32_IRQ_UCPD1);
+
 	/*
 	* After exiting reset, stm32gx will have dead battery mode enabled by
 	* default which connects Rd to CC1/CC2. This should be disabled when EC
@@ -439,6 +451,8 @@ int stm32gx_ucpd_init(int port)
 	/* SOP'/SOP'' must be enabled via TCPCI call */
 	ucpd_rx_sop_prime_enabled = false;
 
+	stm32gx_ucpd_state_init(port);
+
 	/* Enable UCPD interrupts */
 	task_enable_irq(STM32_IRQ_UCPD1);
 
@@ -904,10 +918,7 @@ void ucpd_task(void *p)
 	const int port = (int) ((intptr_t) p);
 
 	/* Init variables used to manage tx process */
-	ucpd_tx_request = 0;
-	tx_retry_count = 0;
-	ucpd_tx_state = STATE_IDLE;
-	ucpd_timeout_us = -1;
+	stm32gx_ucpd_state_init(port);
 
 	while (1) {
 		/*
@@ -1344,11 +1355,16 @@ static int command_ucpd(int argc, char **argv)
 	if (!strcasecmp(argv[1], "rst")) {
 		/* Force reset of ucpd peripheral */
 		stm32gx_ucpd_init(port);
+		pd_execute_hard_reset(port);
+		task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
 	} else if (!strcasecmp(argv[1], "info")) {
 		ucpd_info(port);
 	} else if (!strcasecmp(argv[1], "bist")) {
-		stm32gx_ucpd_transmit(port, TCPC_TX_BIST_MODE_2, 0,
-				      &tx_data);
+		/* Need to initiate via DPM to have a timer */
+		/* TODO(b/182861002): uncomment when Gingerbread has
+		 * full PD support landed.
+		 * pd_dpm_request(port, DPM_REQUEST_BIST_TX);
+		 */
 	} else if (!strcasecmp(argv[1], "hard")) {
 		stm32gx_ucpd_transmit(port, TCPC_TX_HARD_RESET, 0,
 				      &tx_data);
diff --git a/driver/tcpm/stm32gx.c b/driver/tcpm/stm32gx.c
index 0606668abe..b71fe3660c 100644
--- a/driver/tcpm/stm32gx.c
+++ b/driver/tcpm/stm32gx.c
@@ -127,6 +127,20 @@ static void stm32gx_tcpm_sw_reset(void)
 }
 DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, stm32gx_tcpm_sw_reset, HOOK_PRIO_DEFAULT);
 
+static int stm32gx_tcpm_reset_bist_type_2(int port)
+{
+	/*
+	 * The UCPD peripheral must be disabled, then enabled, to recover from
+	 * starting BIST type-2 mode. Call the init method to accomplish
+	 * this. Then, need to send a hard reset to port partner.
+	 */
+	stm32gx_ucpd_init(port);
+	pd_execute_hard_reset(port);
+	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
+
+	return EC_SUCCESS;
+}
+
 const struct tcpm_drv stm32gx_tcpm_drv = {
 	.init			= &stm32gx_tcpm_init,
 	.release		= &stm32gx_tcpm_release,
@@ -143,4 +157,5 @@ const struct tcpm_drv stm32gx_tcpm_drv = {
 	.get_message_raw	= &stm32gx_tcpm_get_message_raw,
 	.transmit		= &stm32gx_tcpm_transmit,
 	.get_chip_info		= &stm32gx_tcpm_get_chip_info,
+	.reset_bist_type_2	= &stm32gx_tcpm_reset_bist_type_2,
 };