Strago: Spi support added on Private SPI lines

BUG=None
TEST=Tested on Braswell Reference Design
BRANCH=None

Change-Id: Idc064e1af837e5e6a1bf4174885bd10624f463d2
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/226297
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Divya Jyothi <zdivyajyothi@gmail.com>
Tested-by: Divya Jyothi <zdivyajyothi@gmail.com>

4 files changed, 35 insertions, 11 deletions

diff --git a/board/strago/board.h b/board/strago/board.h
index fb28504850..4e965b791f 100644
--- a/board/strago/board.h
+++ b/board/strago/board.h
@@ -22,6 +22,11 @@
 #define CONFIG_POWER_COMMON
 #define CONFIG_EXTPOWER_GPIO
 
+#define CONFIG_SPI
+#define CONFIG_SPI_PORT 1
+#define CONFIG_SPI_CS_GPIO GPIO_PVT_CS0
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SIZE 4194304
 /* Modules we want to exclude */
 #undef CONFIG_EEPROM
 #undef CONFIG_EOPTION
@@ -33,10 +38,6 @@
 #undef CONFIG_FANS
 #undef CONFIG_ADC
 #undef CONFIG_WAKE_PIN
-#undef CONFIG_SPI
-#undef CONFIG_SPI_PORT
-#undef CONFIG_SPI_CS_GPIO
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
diff --git a/board/strago/gpio.inc b/board/strago/gpio.inc
index ab33ba9d8e..3244f6fc63 100644
--- a/board/strago/gpio.inc
+++ b/board/strago/gpio.inc
@@ -31,7 +31,7 @@ UNIMPLEMENTED(PCH_RCIN_L)
 GPIO(PCH_SMI_L,         PORT(4),  4, GPIO_ODR_HIGH,                             NULL)                   /* SMI output */
 GPIO(PCH_WAKE_L,        PORT(6),  6, GPIO_ODR_HIGH,                             NULL)                   /* PCH wake pin */
 GPIO(KBD_KSO2,          PORT(10), 1, GPIO_KB_OUTPUT_COL2,                       NULL)                   /* Negative edge triggered irq. */
-
+GPIO(PVT_CS0,        	PORT(14), 6, GPIO_ODR_HIGH,                             NULL)                   /* SPI PVT Chip select */
 /*
  * Signals which aren't implemented on MEC1322 eval board but we'll
  * emulate anyway, to make it more convenient to debug other code.
@@ -51,3 +51,5 @@ ALTERNATE(PORT(11), 0x9e,     1, MODULE_LPC,           0)
 ALTERNATE(PORT(11), 0x40,     1, MODULE_LPC,           GPIO_INT_BOTH)           /* 116: LRESET# */
 ALTERNATE(PORT(12), 0x01,     1, MODULE_LPC,           0)                       /* 120: LFRAME# */
 ALTERNATE(PORT(5),  0x10,     1, MODULE_SPI,           0)
+ALTERNATE(PORT(16), 0x10,     1, MODULE_SPI,           0)
+ALTERNATE(PORT(15), 0x8,      1, MODULE_SPI,           0)
diff --git a/chip/mec1322/dma.c b/chip/mec1322/dma.c
index c064003544..53e09122af 100644
--- a/chip/mec1322/dma.c
+++ b/chip/mec1322/dma.c
@@ -29,6 +29,9 @@ void dma_disable(enum dma_channel channel)
 
 	if (chan->ctrl & (1 << 0))
 		chan->ctrl &= ~(1 << 0);
+
+	if (chan->act == 1)
+		chan->act = 0;
 }
 
 /**
@@ -83,7 +86,9 @@ void dma_prepare_tx(const struct dma_option *option, unsigned count,
 void dma_start_rx(const struct dma_option *option, unsigned count,
 		  void *memory)
 {
-	mec1322_dma_chan_t *chan = dma_get_channel(option->channel);
+	mec1322_dma_chan_t *chan;
+
+	chan = dma_get_channel(option->channel);
 
 	prepare_channel(chan, count, option->periph, memory,
 			MEC1322_DMA_INC_MEM | MEC1322_DMA_DEV(option->channel) |
@@ -111,6 +116,9 @@ int dma_wait(enum dma_channel channel)
 	mec1322_dma_chan_t *chan = dma_get_channel(channel);
 	timestamp_t deadline;
 
+	if (chan->act == 0)
+		return EC_SUCCESS;
+
 	deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US;
 	while (!(chan->int_status & 0x4)) {
 		if (deadline.val <= get_time().val)
diff --git a/chip/mec1322/spi.c b/chip/mec1322/spi.c
index 86d44e639d..b624e04863 100644
--- a/chip/mec1322/spi.c
+++ b/chip/mec1322/spi.c
@@ -13,6 +13,7 @@
 #include "spi.h"
 #include "timer.h"
 #include "util.h"
+#include "hooks.h"
 
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
 #define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
@@ -23,7 +24,7 @@
 #define SPI_DMA_CHANNEL (MEC1322_DMAC_SPI0_RX + CONFIG_SPI_PORT * 2)
 
 static const struct dma_option spi_rx_option = {
-	SPI_DMA_CHANNEL, (void *)&MEC1322_SPI_RD(0),
+	SPI_DMA_CHANNEL, (void *)&MEC1322_SPI_RD(CONFIG_SPI_PORT),
 	MEC1322_DMA_XFER_SIZE(1)
 };
 
@@ -74,9 +75,10 @@ int spi_transaction_async(const uint8_t *txdata, int txlen,
 	/* Enable auto read */
 	MEC1322_SPI_CR(CONFIG_SPI_PORT) |= 1 << 5;
 
-	dma_start_rx(&spi_rx_option, rxlen, rxdata);
-	MEC1322_SPI_TD(CONFIG_SPI_PORT) = 0;
-
+	if (rxlen != 0) {
+		dma_start_rx(&spi_rx_option, rxlen, rxdata);
+		MEC1322_SPI_TD(CONFIG_SPI_PORT) = 0;
+	}
 	return ret;
 }
 
@@ -85,16 +87,26 @@ int spi_transaction_flush(void)
 	int ret = dma_wait(SPI_DMA_CHANNEL);
 	uint8_t dummy __attribute__((unused)) = 0;
 
+	timestamp_t deadline;
+
 	/* Disable auto read */
 	MEC1322_SPI_CR(CONFIG_SPI_PORT) &= ~(1 << 5);
 
-	gpio_set_level(CONFIG_SPI_CS_GPIO, 1);
+	deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US;
+	/* Wait for FIFO empty SPISR_TXBE */
+	while ((MEC1322_SPI_SR(CONFIG_SPI_PORT) & 0x01) != 0x1) {
+		if (timestamp_expired(deadline, NULL))
+			return EC_ERROR_TIMEOUT;
+		usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US);
+	}
 
 	dma_disable(SPI_DMA_CHANNEL);
 	dma_clear_isr(SPI_DMA_CHANNEL);
 	if (MEC1322_SPI_SR(CONFIG_SPI_PORT) & 0x2)
 		dummy = MEC1322_SPI_RD(CONFIG_SPI_PORT);
 
+	gpio_set_level(CONFIG_SPI_CS_GPIO, 1);
+
 	return ret;
 }
 
@@ -134,3 +146,4 @@ int spi_enable(int enable)
 
 	return EC_SUCCESS;
 }
+