rt1718s: enable FRS

BUG=b:190348051
TEST=Combined with other CLs in the chain, verify FRS workable on Tomato
BRANCH=none

Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I52a020b1288928eb9a0f3ada1364776cd8e78337
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3109709
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>

3 files changed, 75 insertions, 10 deletions

diff --git a/driver/ppc/rt1718s.c b/driver/ppc/rt1718s.c
index 8fb9200cb1..96cb789cd0 100644
--- a/driver/ppc/rt1718s.c
+++ b/driver/ppc/rt1718s.c
@@ -173,6 +173,12 @@ static int rt1718s_init(int port)
 {
 	atomic_clear(&flags[port]);
 
+	if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC))
+		/* Set Rx frs unmasked */
+		RETURN_ERROR(update_bits(port, RT1718S_RT_MASK1,
+					RT1718S_RT_MASK1_M_RX_FRS,
+					0xFF));
+
 	return EC_SUCCESS;
 }
 
@@ -183,6 +189,29 @@ static int rt1718s_set_polarity(int port, int polarity)
 }
 #endif
 
+#ifdef CONFIG_USB_PD_FRS_PPC
+static int rt1718s_set_frs_enable(int port, int enable)
+{
+	/*
+	 * Use write instead of update to save 2 i2c read.
+	 * Assume other bits are at their reset value.
+	 */
+	int frs_ctrl2 = 0x10, vbus_ctrl_en = 0x3F;
+
+	if (enable) {
+		frs_ctrl2 |= RT1718S_FRS_CTRL2_RX_FRS_EN;
+		frs_ctrl2 |= RT1718S_FRS_CTRL2_VBUS_FRS_EN;
+
+		vbus_ctrl_en |= RT1718S_VBUS_CTRL_EN_GPIO2_VBUS_PATH_EN;
+		vbus_ctrl_en |= RT1718S_VBUS_CTRL_EN_GPIO1_VBUS_PATH_EN;
+	}
+
+	RETURN_ERROR(write_reg(port, RT1718S_FRS_CTRL2, frs_ctrl2));
+	RETURN_ERROR(write_reg(port, RT1718S_VBUS_CTRL_EN, vbus_ctrl_en));
+	return EC_SUCCESS;
+}
+#endif
+
 const struct ppc_drv rt1718s_ppc_drv = {
 	.init = &rt1718s_init,
 	.is_sourcing_vbus = &rt1718s_is_sourcing_vbus,
@@ -202,4 +231,7 @@ const struct ppc_drv rt1718s_ppc_drv = {
 #ifdef CONFIG_USBC_PPC_VCONN
 	.set_vconn = &tcpci_tcpm_set_vconn,
 #endif
+#ifdef CONFIG_USB_PD_FRS_PPC
+	.set_frs_enable = rt1718s_set_frs_enable,
+#endif
 };
diff --git a/driver/tcpm/rt1718s.c b/driver/tcpm/rt1718s.c
index 96a08785c2..ca5151ba90 100644
--- a/driver/tcpm/rt1718s.c
+++ b/driver/tcpm/rt1718s.c
@@ -224,14 +224,6 @@ static int rt1718s_init(int port)
 		need_sw_reset = false;
 	}
 
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC))
-		/* Set vbus frs low unmasked, Rx frs unmasked */
-		RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT_MASK1,
-					RT1718S_RT_MASK1_M_VBUS_FRS_LOW |
-					RT1718S_RT_MASK1_M_RX_FRS,
-					0xFF));
-
-
 	RETURN_ERROR(rt1718s_bc12_init(port));
 
 	/* Set VBUS_VOL_SEL to 20V */
@@ -357,6 +349,27 @@ void rt1718s_vendor_defined_alert(int port)
 {
 	int rv, value;
 
+	if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC) &&
+	    IS_ENABLED(CONFIG_USBC_PPC_RT1718S)) {
+		int int1;
+
+		rv = rt1718s_read8(port, RT1718S_RT_INT1, &int1);
+		if (rv)
+			return;
+		rv = rt1718s_write8(port, RT1718S_RT_INT1, int1);
+		if (rv)
+			return;
+
+		if ((int1 & RT1718S_RT_INT1_INT_RX_FRS)) {
+			pd_got_frs_signal(port);
+
+			tcpc_write16(port, TCPC_REG_ALERT,
+					TCPC_REG_ALERT_VENDOR_DEF);
+			/* ignore other interrupts for faster frs handling */
+			return;
+		}
+	}
+
 	/* Process BC12 alert */
 	rv = rt1718s_read8(port, RT1718S_RT_INT6, &value);
 	if (rv)
@@ -393,7 +406,9 @@ static void rt1718s_alert(int port)
 	tcpc_read16(port, TCPC_REG_ALERT, &alert);
 	if (alert & TCPC_REG_ALERT_VENDOR_DEF)
 		rt1718s_vendor_defined_alert(port);
-	tcpci_tcpc_alert(port);
+
+	if (alert & ~TCPC_REG_ALERT_VENDOR_DEF)
+		tcpci_tcpc_alert(port);
 }
 
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
diff --git a/driver/tcpm/rt1718s.h b/driver/tcpm/rt1718s.h
index 9aed749440..3bc5696fd7 100644
--- a/driver/tcpm/rt1718s.h
+++ b/driver/tcpm/rt1718s.h
@@ -54,6 +54,9 @@
 #define RT1718S_RT_MASK6_M_BC12_TA_CHG			BIT(5)
 #define RT1718S_RT_MASK7				0x97
 
+#define RT1718S_RT_INT1					0x98
+#define RT1718S_RT_INT1_INT_VBUS_FRS_LOW		BIT(7)
+#define RT1718S_RT_INT1_INT_RX_FRS			BIT(6)
 #define RT1718S_RT_INT2					0x99
 #define RT1718S_RT_INT6					0x9D
 #define RT1718S_RT_INT6_INT_BC12_SNK_DONE		BIT(7)
@@ -80,14 +83,29 @@
 
 #define RT1718S_HILO_CTRL9				0xC8
 #define RT1718S_SHILED_CTRL1				0xCA
+#define RT1718S_FRS_CTRL1				0xCB
+#define RT1718S_FRS_CTRL1_FRSWAPRX_MASK			0xF0
+#define RT1718S_FRS_CTRL2				0xCC
+#define RT1718S_FRS_CTRL2_RX_FRS_EN			BIT(6)
+#define RT1718S_FRS_CTRL2_FR_VBUS_SELECT		BIT(4)
+#define RT1718S_FRS_CTRL2_VBUS_FRS_EN			BIT(3)
+#define RT1718S_FRS_CTRL3				0xCE
+#define RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2		BIT(3)
+#define RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1		BIT(2)
 
 #define RT1718S_DIS_SRC_VBUS_CTRL			0xE0
 #define RT1718S_ENA_SRC_VBUS_CTRL			0xE1
 #define RT1718S_FAULT_OC1_VBUS_CTRL			0xE3
+#define RT1718S_GPIO1_VBUS_CTRL				0xEA
+#define RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS		BIT(6)
 #define RT1718S_GPIO2_VBUS_CTRL				0xEB
-
+#define RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS		BIT(6)
+#define RT1718S_VBUS_CTRL_EN				0xEC
+#define RT1718S_VBUS_CTRL_EN_GPIO2_VBUS_PATH_EN		BIT(7)
+#define RT1718S_VBUS_CTRL_EN_GPIO1_VBUS_PATH_EN		BIT(6)
 #define RT1718S_GPIO1_CTRL				0xED
 #define RT1718S_GPIO2_CTRL				0xEE
+#define RT1718S_GPIO3_CTRL				0xEF
 #define RT1718S_GPIOX_OD_N				BIT(3)
 #define RT1718S_GPIOX_OE				BIT(2)
 #define RT1718S_GPIOX_CTRL_GPIOX_O			BIT(1)