chip/stm32: Remove unwanted protool extension

This first attempt turned out to be too closely coupled to the
capabilities of the STM32L5xx OctoSPI, allowing odd combiations that is
never used by actual SPI flash chips.

BUG=b:273601311
TEST=make BOARD=c2d2

Change-Id: I3fd5b1356d1c2c3a7d63dbdf8e1a5fd45ddfe0a1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4432090
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
Tested-by: Jes Klinke <jbk@chromium.org>

1 files changed, 0 insertions, 85 deletions

diff --git a/chip/stm32/usb_spi.h b/chip/stm32/usb_spi.h
index 385aaaf730..90c15f5f65 100644
--- a/chip/stm32/usb_spi.h
+++ b/chip/stm32/usb_spi.h
@@ -661,89 +661,4 @@ int usb_spi_board_transaction(const struct spi_device_t *spi_device,
 			      uint32_t flash_flags, const uint8_t *txdata,
 			      int txlen, uint8_t *rxdata, int rxlen);
 
-/*
- * Flags to use in usb_spi_board_transaction_async() for advanced serial flash
- * communication, when supported.
- */
-
-/* Data width during the opcode stage. */
-#define FLASH_FLAG_OPCODE_WIDTH_POS 0
-#define FLASH_FLAG_OPCODE_WIDTH_MSK (0x3U << FLASH_FLAG_OPCODE_WIDTH_POS)
-#define FLASH_FLAG_OPCODE_WIDTH_1WIRE (0x0U << FLASH_FLAG_OPCODE_WIDTH_POS)
-#define FLASH_FLAG_OPCODE_WIDTH_2WIRE (0x1U << FLASH_FLAG_OPCODE_WIDTH_POS)
-#define FLASH_FLAG_OPCODE_WIDTH_4WIRE (0x2U << FLASH_FLAG_OPCODE_WIDTH_POS)
-#define FLASH_FLAG_OPCODE_WIDTH_8WIRE (0x3U << FLASH_FLAG_OPCODE_WIDTH_POS)
-
-/* Transmit opcode bits at both rising and falling clock edges. */
-#define FLASH_FLAG_OPCODE_DTR_POS 2
-#define FLASH_FLAG_OPCODE_DTR (0x1U << FLASH_FLAG_OPCODE_DTR_POS)
-
-/* Number of bytes of opcode (0-4). */
-#define FLASH_FLAG_OPCODE_LEN_POS 3
-#define FLASH_FLAG_OPCODE_LEN_MSK (0x7U << FLASH_FLAG_OPCODE_LEN_POS)
-
-/* Data width during the address stage. */
-#define FLASH_FLAG_ADDR_WIDTH_POS 6
-#define FLASH_FLAG_ADDR_WIDTH_MSK (0x3U << FLASH_FLAG_ADDR_WIDTH_POS)
-#define FLASH_FLAG_ADDR_WIDTH_1WIRE (0x0U << FLASH_FLAG_ADDR_WIDTH_POS)
-#define FLASH_FLAG_ADDR_WIDTH_2WIRE (0x1U << FLASH_FLAG_ADDR_WIDTH_POS)
-#define FLASH_FLAG_ADDR_WIDTH_4WIRE (0x2U << FLASH_FLAG_ADDR_WIDTH_POS)
-#define FLASH_FLAG_ADDR_WIDTH_8WIRE (0x3U << FLASH_FLAG_ADDR_WIDTH_POS)
-
-/* Transmit address bits at both rising and falling clock edges. */
-#define FLASH_FLAG_ADDR_DTR_POS 8
-#define FLASH_FLAG_ADDR_DTR (0x1U << FLASH_FLAG_ADDR_DTR_POS)
-
-/* Number of bytes of address (0-4). */
-#define FLASH_FLAG_ADDR_LEN_POS 9
-#define FLASH_FLAG_ADDR_LEN_MSK (0x7U << FLASH_FLAG_ADDR_LEN_POS)
-
-/* Data width during the "alternate bytes" stage. */
-#define FLASH_FLAG_ALT_WIDTH_POS 12
-#define FLASH_FLAG_ALT_WIDTH_MSK (0x3U << FLASH_FLAG_ALT_WIDTH_POS)
-#define FLASH_FLAG_ALT_WIDTH_1WIRE (0x0U << FLASH_FLAG_ALT_WIDTH_POS)
-#define FLASH_FLAG_ALT_WIDTH_2WIRE (0x1U << FLASH_FLAG_ALT_WIDTH_POS)
-#define FLASH_FLAG_ALT_WIDTH_4WIRE (0x2U << FLASH_FLAG_ALT_WIDTH_POS)
-#define FLASH_FLAG_ALT_WIDTH_8WIRE (0x3U << FLASH_FLAG_ALT_WIDTH_POS)
-
-/* Transmit alternate bits at both rising and falling clock edges. */
-#define FLASH_FLAG_ALT_DTR_POS 14
-#define FLASH_FLAG_ALT_DTR (0x1U << FLASH_FLAG_ALT_DTR_POS)
-
-/* Number of bytes of alternate data (0-4). */
-#define FLASH_FLAG_ALT_LEN_POS 15
-#define FLASH_FLAG_ALT_LEN_MSK (0x7U << FLASH_FLAG_ALT_LEN_POS)
-
-/* Number of dummy clock cycles (0-31). */
-#define FLASH_FLAG_DUMMY_CYCLES_POS 18
-#define FLASH_FLAG_DUMMY_CYCLES_MSK (0x1FU << FLASH_FLAG_DUMMY_CYCLES_POS)
-
-/* Data width during the data stage. */
-#define FLASH_FLAG_DATA_WIDTH_POS 23
-#define FLASH_FLAG_DATA_WIDTH_MSK (0x3U << FLASH_FLAG_DATA_WIDTH_POS)
-#define FLASH_FLAG_DATA_WIDTH_1WIRE (0x0U << FLASH_FLAG_DATA_WIDTH_POS)
-#define FLASH_FLAG_DATA_WIDTH_2WIRE (0x1U << FLASH_FLAG_DATA_WIDTH_POS)
-#define FLASH_FLAG_DATA_WIDTH_4WIRE (0x2U << FLASH_FLAG_DATA_WIDTH_POS)
-#define FLASH_FLAG_DATA_WIDTH_8WIRE (0x3U << FLASH_FLAG_DATA_WIDTH_POS)
-
-/* Transmit data bits at both rising and falling clock edges. */
-#define FLASH_FLAG_DATA_DTR_POS 25
-#define FLASH_FLAG_DATA_DTR (0x1U << FLASH_FLAG_DATA_DTR_POS)
-
-/*
- * Mask of the flags that cannot be ignored.  This is basically any flags
- * which call for wires to switch direction, or data being clocked on both
- * rising and falling edges.  As long as none of these are present, then the
- * remaining flags specifying the length of opcode/address can be ignored, as
- * the entire data buffer can be transmitted as a sequence of bytes, without
- * the controller knowing which parts are to be interpreted as
- * opcode/address/data.
- */
-#define FLASH_FLAGS_REQUIRING_SUPPORT                              \
-	(FLASH_FLAG_OPCODE_WIDTH_MSK | FLASH_FLAG_OPCODE_DTR |     \
-	 FLASH_FLAG_ADDR_WIDTH_MSK | FLASH_FLAG_ADDR_DTR |         \
-	 FLASH_FLAG_ALT_WIDTH_MSK | FLASH_FLAG_ALT_DTR |           \
-	 FLASH_FLAG_DUMMY_CYCLES_MSK | FLASH_FLAG_DATA_WIDTH_MSK | \
-	 FLASH_FLAG_DATA_DTR)
-
 #endif /* __CROS_EC_USB_SPI_H */